From 89ac5ba11c773764f418c92ab47a237287a0d233 Mon Sep 17 00:00:00 2001 From: Eli Zaretskii Date: Sat, 1 Apr 2023 13:07:42 +0300 Subject: [PATCH] Fix ModelSim error regexp in vhdl-mode * lisp/progmodes/vhdl-mode.el (vhdl-compiler-alist): Fix ModelSim error regexp. Suggested by Reto Zimmermann . (Bug#62508) --- lisp/progmodes/vhdl-mode.el | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lisp/progmodes/vhdl-mode.el b/lisp/progmodes/vhdl-mode.el index c5ab5013fc8..b0699d8308b 100644 --- a/lisp/progmodes/vhdl-mode.el +++ b/lisp/progmodes/vhdl-mode.el @@ -286,7 +286,7 @@ Overrides local variable `indent-tabs-mode'." ;; counter_rtl.vhd(29):Conditional signal assignment line__29 ("ModelSim" "vcom" "-93 -work \\1" "make" "-f \\1" nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "modelsim" - ("\\(ERROR:\\|WARNING\\[[0-9]+\\]:\\|\\*\\* Error:\\|\\*\\* Warning: \\[[0-9]+\\]\\| +\\) \\([^ ]+\\)(\\([0-9]+\\)):" 2 3 nil) + ("^\\(ERROR\\|WARNING\\|\\*\\* Error\\|\\*\\* Warning\\)[^:]*:\\( *\[[0-9]+\]\\| ([^)]+)\\)? \\([^ \t\n]+\\)(\\([0-9]+\\)):" 3 4 nil) ("" 0) ("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat" "\\1/_primary.dat" "\\1/body.dat" downcase)) -- 2.39.2