From 6dfe231c3197971fc0cdddcc1299200da80f3729 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Mattias=20Engdeg=C3=A5rd?= Date: Sun, 7 Apr 2019 20:50:40 +0200 Subject: [PATCH] Rename variable for clarity * lisp/progmodes/verilog-mode.el (verilog-sk-define-signal): Rename sig-re to sig-chars, to make it clear that it isn't a regexp. --- lisp/progmodes/verilog-mode.el | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el index 916594bdde0..9226291ffbb 100644 --- a/lisp/progmodes/verilog-mode.el +++ b/lisp/progmodes/verilog-mode.el @@ -14263,13 +14263,13 @@ and the case items." (defun verilog-sk-define-signal () "Insert a definition of signal under point at top of module." (interactive "*") - (let* ((sig-re "a-zA-Z0-9_") + (let* ((sig-chars "a-zA-Z0-9_") (v1 (buffer-substring (save-excursion - (skip-chars-backward sig-re) + (skip-chars-backward sig-chars) (point)) (save-excursion - (skip-chars-forward sig-re) + (skip-chars-forward sig-chars) (point))))) (if (not (member v1 verilog-keywords)) (save-excursion -- 2.39.2