From 470864957479aac7eaef9958974909fb34c83e24 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 3 May 2012 15:23:55 -0400 Subject: [PATCH] Merge verilog-mode.el from upstream. * progmodes/verilog-mode.el (font-lock-keywords): Fix mis-highligting auto. Reported by Craig Barner. (verilog-auto, verilog-auto-undef): Add AUTOUNDEF to remove defines from global name space. Reported by Dan Dever. (verilog-auto-reset, verilog-auto-reset-widths) (verilog-auto-tieoff): Support using unbased numbers for AUTORESET and AUTOTIEOFF. (verilog-submit-bug-report): Update variable list. (verilog-read-auto-params): Fix AUTOINPUT regexps containing parenthesis from not matching. Reported by Michael Rytting. (verilog-auto-template-lint): Fix hash error when linting modules with no used templates. (verilog-warn, verilog-warn-error) (verilog-warn-fatal): When non-interactive report multiple warnings before exiting. Suggested by Brad Dobbie. (verilog-auto-template-lint, verilog-auto-template-warn-unused) (verilog-read-auto-template): Add `verilog-auto-template-warn-unused' to report unused template errors. Reported by Brad Dobbie. (verilog-read-decls): Fix AUTOWIRE etc on supply0, supply1 type nets, bug438. Reported by Vns Blore. (verilog-auto-inout-module, verilog-auto-reg) (verilog-read-decls, verilog-read-sub-decls-sig) (verilog-signals-edit-wire-reg, verilog-signals-with): Fix passing of Verilog data types in ANSI input/output ports such as "output logic" into the AUTOs. Special case "wire" and "reg" for backwards compatibility presuming Verilog 2001. (verilog-auto-ascii-enum): Add "auto enum" as alias. (verilog-preprocess): Fix replication of preprocess output. Reported by Brad Dobbie. (verilog-auto-inst-interfaced-ports): Create verilog-auto-inst-interfaced-ports, bug429. Reported by Julian Gorfajn. (verilog-after-save-font-hook) (verilog-before-save-font-hook): New variable. (verilog-modi-cache-results, verilog-save-font-mod-hooked) (verilog-save-font-mods): Wrap disabling fontification, reported by David Rogoff. (verilog-do-indent, verilog-pretty-declarations-auto) (verilog-sk-def-reg): Fix obeying `verilog-auto-lineup', bug305. Reported by Pierre-David Pfister. (verilog-set-auto-endcomments): Fix endtask auto comments outside of class declarations, bug292. Reported by Kevin Heilman. (verilog-read-decls): Fix 'parameter type' not appearing in AUTOINSTPARAM, bug340. Reported by Jonathan Greenlaw. (verilog-auto-logic): Fix when AUTOLOGIC present to properly do AUTOINPUTs, bug411. Reported by Jonathan Greenlaw. (verilog-read-auto-lisp): Avoid syntax-ppss warning on AUTOLISP. Reported by David Kravitz. * progmodes/verilog-mode.el (verilog-pretty-expr): Don't line up assignment with tests in ifs and for loops. (verilog-extended-complete-re, verilog-complete-reg): Change so that DPI inport functions don't look like fuction declarations. (verilog-pretty-expr): Don't line up assignment operations to the test and increment in if and for loops (verilog-extended-complete-re, verilog-complete-reg): Change so that DPI inport functions don't look like fuction declarations --- lisp/ChangeLog | 62 ++ lisp/progmodes/verilog-mode.el | 1174 ++++++++++++++++++++------------ 2 files changed, 811 insertions(+), 425 deletions(-) diff --git a/lisp/ChangeLog b/lisp/ChangeLog index ff2c5a40787..96273f72ece 100644 --- a/lisp/ChangeLog +++ b/lisp/ChangeLog @@ -1,3 +1,65 @@ +2012-05-03 Wilson Snyder + + * progmodes/verilog-mode.el (font-lock-keywords): + Fix mis-highligting auto. Reported by Craig Barner. + (verilog-auto, verilog-auto-undef): Add AUTOUNDEF to remove + defines from global name space. Reported by Dan Dever. + (verilog-auto-reset, verilog-auto-reset-widths) + (verilog-auto-tieoff): Support using unbased numbers for + AUTORESET and AUTOTIEOFF. + (verilog-submit-bug-report): Update variable list. + (verilog-read-auto-params): Fix AUTOINPUT regexps containing + parenthesis from not matching. Reported by Michael Rytting. + (verilog-auto-template-lint): Fix hash error when linting modules + with no used templates. + (verilog-warn, verilog-warn-error) + (verilog-warn-fatal): When non-interactive report multiple + warnings before exiting. Suggested by Brad Dobbie. + (verilog-auto-template-lint, verilog-auto-template-warn-unused) + (verilog-read-auto-template): Add `verilog-auto-template-warn-unused' + to report unused template errors. Reported by Brad Dobbie. + (verilog-read-decls): Fix AUTOWIRE etc on supply0, supply1 type + nets, bug438. Reported by Vns Blore. + (verilog-auto-inout-module, verilog-auto-reg) + (verilog-read-decls, verilog-read-sub-decls-sig) + (verilog-signals-edit-wire-reg, verilog-signals-with): + Fix passing of Verilog data types in ANSI input/output ports + such as "output logic" into the AUTOs. Special case "wire" and + "reg" for backwards compatibility presuming Verilog 2001. + (verilog-auto-ascii-enum): Add "auto enum" as alias. + (verilog-preprocess): Fix replication of preprocess output. + Reported by Brad Dobbie. + (verilog-auto-inst-interfaced-ports): + Create verilog-auto-inst-interfaced-ports, bug429. + Reported by Julian Gorfajn. + (verilog-after-save-font-hook) + (verilog-before-save-font-hook): New variable. + (verilog-modi-cache-results, verilog-save-font-mod-hooked) + (verilog-save-font-mods): Wrap disabling fontification, reported + by David Rogoff. + (verilog-do-indent, verilog-pretty-declarations-auto) + (verilog-sk-def-reg): Fix obeying `verilog-auto-lineup', bug305. + Reported by Pierre-David Pfister. + (verilog-set-auto-endcomments): Fix endtask auto comments outside + of class declarations, bug292. Reported by Kevin Heilman. + (verilog-read-decls): Fix 'parameter type' not appearing in + AUTOINSTPARAM, bug340. Reported by Jonathan Greenlaw. + (verilog-auto-logic): Fix when AUTOLOGIC present to properly do + AUTOINPUTs, bug411. Reported by Jonathan Greenlaw. + (verilog-read-auto-lisp): Avoid syntax-ppss warning on AUTOLISP. + Reported by David Kravitz. + +2012-05-03 Michael McNamara + + * progmodes/verilog-mode.el (verilog-pretty-expr): Don't line up + assignment with tests in ifs and for loops. + (verilog-extended-complete-re, verilog-complete-reg): Change so + that DPI inport functions don't look like fuction declarations. + (verilog-pretty-expr): Don't line up assignment + operations to the test and increment in if and for loops + (verilog-extended-complete-re, verilog-complete-reg): Change so + that DPI inport functions don't look like fuction declarations + 2012-05-03 Kenichi Handa * mail/rmailmm.el (rmail-show-mime): Catch an error caused by text diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el index ad1dae9acf9..0cd8d01aff1 100644 --- a/lisp/progmodes/verilog-mode.el +++ b/lisp/progmodes/verilog-mode.el @@ -123,9 +123,9 @@ ;;; Code: ;; This variable will always hold the version number of the mode -(defconst verilog-mode-version "725" +(defconst verilog-mode-version "800" "Version of this Verilog mode.") -(defconst verilog-mode-release-date "2011-11-27-GNU" +(defconst verilog-mode-release-date "2012-04-23-GNU" "Release date of this Verilog mode.") (defconst verilog-mode-release-emacs t "If non-nil, this version of Verilog mode was released with Emacs itself.") @@ -415,7 +415,10 @@ Set `verilog-in-hooks' during this time, to assist AUTO caches." :group 'verilog-mode) (defvar verilog-debug nil - "If set, enable debug messages for `verilog-mode' internals.") + "Non-nil means enable debug messages for `verilog-mode' internals.") + +(defvar verilog-warn-fatal nil + "Non-nil means `verilog-warn-error' warnings are fatal `error's.") (defcustom verilog-linter "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'" @@ -524,6 +527,8 @@ are lineup only when \\[verilog-pretty-declarations] is typed." (const :tag "Line up Declarations" declarations) (function :tag "Other")) :group 'verilog-mode-indent ) +(put 'verilog-auto-lineup 'safe-local-variable + '(lambda (x) (memq x '(nil all assignments declarations)))) (defcustom verilog-indent-level 3 "Indentation of Verilog statements with respect to containing block." @@ -600,40 +605,39 @@ Set to 0 to have all directives start at the left side of the screen." (put 'verilog-case-indent 'safe-local-variable 'integerp) (defcustom verilog-auto-newline t - "True means automatically newline after semicolons." + "Non-nil means automatically newline after semicolons." :group 'verilog-mode-indent :type 'boolean) (put 'verilog-auto-newline 'safe-local-variable 'verilog-booleanp) (defcustom verilog-auto-indent-on-newline t - "True means automatically indent line after newline." + "Non-nil means automatically indent line after newline." :group 'verilog-mode-indent :type 'boolean) (put 'verilog-auto-indent-on-newline 'safe-local-variable 'verilog-booleanp) (defcustom verilog-tab-always-indent t - "True means TAB should always re-indent the current line. + "Non-nil means TAB should always re-indent the current line. A nil value means TAB will only reindent when at the beginning of the line." :group 'verilog-mode-indent :type 'boolean) (put 'verilog-tab-always-indent 'safe-local-variable 'verilog-booleanp) (defcustom verilog-tab-to-comment nil - "True means TAB moves to the right hand column in preparation for a comment." + "Non-nil means TAB moves to the right hand column in preparation for a comment." :group 'verilog-mode-actions :type 'boolean) (put 'verilog-tab-to-comment 'safe-local-variable 'verilog-booleanp) (defcustom verilog-indent-begin-after-if t - "If true, indent begin statements following if, else, while, for and repeat. + "Non-nil means indent begin statements following if, else, while, etc. Otherwise, line them up." :group 'verilog-mode-indent :type 'boolean) (put 'verilog-indent-begin-after-if 'safe-local-variable 'verilog-booleanp) - (defcustom verilog-align-ifelse nil - "If true, align `else' under matching `if'. + "Non-nil means align `else' under matching `if'. Otherwise else is lined up with first character on line holding matching if." :group 'verilog-mode-indent :type 'boolean) @@ -648,7 +652,7 @@ default avoids too many redundant comments in tight quarters." (put 'verilog-minimum-comment-distance 'safe-local-variable 'integerp) (defcustom verilog-highlight-p1800-keywords nil - "True means highlight words newly reserved by IEEE-1800. + "Non-nil means highlight words newly reserved by IEEE-1800. These will appear in `verilog-font-lock-p1800-face' in order to gently suggest changing where these words are used as variables to something else. A nil value means highlight these words as appropriate for the SystemVerilog @@ -659,7 +663,7 @@ to see the effect as font color choices are cached by Emacs." (put 'verilog-highlight-p1800-keywords 'safe-local-variable 'verilog-booleanp) (defcustom verilog-highlight-grouping-keywords nil - "True means highlight grouping keywords 'begin' and 'end' more dramatically. + "Non-nil means highlight grouping keywords 'begin' and 'end' more dramatically. If false, these words are in the `font-lock-type-face'; if True then they are in `verilog-font-lock-ams-face'. Some find that special highlighting on these grouping constructs allow the structure of the code to be understood at a glance." @@ -668,7 +672,7 @@ grouping constructs allow the structure of the code to be understood at a glance (put 'verilog-highlight-grouping-keywords 'safe-local-variable 'verilog-booleanp) (defcustom verilog-highlight-modules nil - "True means highlight module statements for `verilog-load-file-at-point'. + "Non-nil means highlight module statements for `verilog-load-file-at-point'. When true, mousing over module names will allow jumping to the module definition. If false, this is not supported. Setting this is experimental, and may lead to bad performance." @@ -677,7 +681,7 @@ this is experimental, and may lead to bad performance." (put 'verilog-highlight-modules 'safe-local-variable 'verilog-booleanp) (defcustom verilog-highlight-includes t - "True means highlight module statements for `verilog-load-file-at-point'. + "Non-nil means highlight module statements for `verilog-load-file-at-point'. When true, mousing over include file names will allow jumping to the file referenced. If false, this is not supported." :group 'verilog-mode-indent @@ -689,7 +693,7 @@ file referenced. If false, this is not supported." Set this to \"wire\" if the Verilog code uses \"`default_nettype none\". Note using `default_nettype none isn't recommended practice; this mode is experimental." - :version "24.1" + :version "24.1" ;; rev670 :group 'verilog-mode-actions :type 'boolean) (put 'verilog-auto-declare-nettype 'safe-local-variable `stringp) @@ -697,27 +701,27 @@ mode is experimental." (defcustom verilog-auto-wire-type nil "Non-nil specifies the data type to use with `verilog-auto-wire' etc. Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'." - :version "24.1" + :version "24.1" ;; rev673 :group 'verilog-mode-actions :type 'boolean) (put 'verilog-auto-wire-type 'safe-local-variable `stringp) (defcustom verilog-auto-endcomments t - "True means insert a comment /* ... */ after 'end's. + "Non-nil means insert a comment /* ... */ after 'end's. The name of the function or case will be set between the braces." :group 'verilog-mode-actions :type 'boolean) (put 'verilog-auto-endcomments 'safe-local-variable 'verilog-booleanp) (defcustom verilog-auto-delete-trailing-whitespace nil - "True means to `delete-trailing-whitespace' in `verilog-auto'." - :version "24.1" + "Non-nil means to `delete-trailing-whitespace' in `verilog-auto'." + :version "24.1" ;; rev703 :group 'verilog-mode-actions :type 'boolean) (put 'verilog-auto-delete-trailing-whitespace 'safe-local-variable 'verilog-booleanp) (defcustom verilog-auto-ignore-concat nil - "True means ignore signals in {...} concatenations for AUTOWIRE etc. + "Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc. This will exclude signals referenced as pin connections in {...} from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set for backward compatibility only and not set in new designs; it @@ -727,7 +731,7 @@ may be removed in future versions." (put 'verilog-auto-ignore-concat 'safe-local-variable 'verilog-booleanp) (defcustom verilog-auto-read-includes nil - "True means to automatically read includes before AUTOs. + "Non-nil means to automatically read includes before AUTOs. This will do a `verilog-read-defines' and `verilog-read-includes' before each AUTO expansion. This makes it easier to embed defines and includes, but can result in very slow reading times if there are many or large @@ -750,15 +754,15 @@ sub-module's port list has changed." :type '(choice (const nil) (const ask) (const detect) (const force))) (defcustom verilog-auto-star-expand t - "Non-nil indicates to expand a SystemVerilog .* instance ports. -They will be expanded in the same way as if there was a AUTOINST in the + "Non-nil means to expand SystemVerilog .* instance ports. +They will be expanded in the same way as if there was an AUTOINST in the instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'." :group 'verilog-mode-actions :type 'boolean) (put 'verilog-auto-star-expand 'safe-local-variable 'verilog-booleanp) (defcustom verilog-auto-star-save nil - "Non-nil indicates to save to disk SystemVerilog .* instance expansions. + "Non-nil means save to disk SystemVerilog .* instance expansions. A nil value indicates direct connections will be removed before saving. Only meaningful to those created due to `verilog-auto-star-expand' being set. @@ -964,7 +968,7 @@ you will probably also need `verilog-auto-reset-widths' set." (put 'verilog-active-low-regexp 'safe-local-variable 'stringp) (defcustom verilog-auto-sense-include-inputs nil - "If true, AUTOSENSE should include all inputs. + "Non-nil means AUTOSENSE should include all inputs. If nil, only inputs that are NOT output signals in the same block are included." :group 'verilog-mode-auto @@ -972,7 +976,7 @@ included." (put 'verilog-auto-sense-include-inputs 'safe-local-variable 'verilog-booleanp) (defcustom verilog-auto-sense-defines-constant nil - "If true, AUTOSENSE should assume all defines represent constants. + "Non-nil means AUTOSENSE should assume all defines represent constants. When true, the defines will not be included in sensitivity lists. To maintain compatibility with other sites, this should be set at the bottom of each Verilog file that requires it, rather than being set globally." @@ -981,28 +985,36 @@ of each Verilog file that requires it, rather than being set globally." (put 'verilog-auto-sense-defines-constant 'safe-local-variable 'verilog-booleanp) (defcustom verilog-auto-reset-blocking-in-non t - "If true, AUTORESET will reset those signals which were -assigned with blocking assignments (=) even in a block with -non-blocking assignments (<=). + "Non-nil means AUTORESET will reset blocking statements. +When true, AUTORESET will reset in blocking statements those +signals which were assigned with blocking assignments (=) even in +a block with non-blocking assignments (<=). If nil, all blocking assigned signals are ignored when any non-blocking assignment is in the AUTORESET block. This allows blocking assignments to be used for temporary values and not have those temporaries reset. See example in `verilog-auto-reset'." - :version "24.1" + :version "24.1" ;; rev718 :type 'boolean :group 'verilog-mode-auto) (put 'verilog-auto-reset-blocking-in-non 'safe-local-variable 'verilog-booleanp) (defcustom verilog-auto-reset-widths t - "If true, AUTORESET should determine the width of signals. + "True means AUTORESET should determine the width of signals. This is then used to set the width of the zero (32'h0 for example). This is required by some lint tools that aren't smart enough to ignore widths of -the constant zero. This may result in ugly code when parameters determine -the MSB or LSB of a signal inside an AUTORESET." +the constant zero. This may result in ugly code when parameters determine +the MSB or LSB of a signal inside an AUTORESET. + +If nil, AUTORESET uses \"0\" as the constant. + +If 'unbased', AUTORESET used the unbased unsized literal \"'0\" +as the constant. This setting is strongly recommended for +SystemVerilog designs." :type 'boolean :group 'verilog-mode-auto) -(put 'verilog-auto-reset-widths 'safe-local-variable 'verilog-booleanp) +(put 'verilog-auto-reset-widths 'safe-local-variable + '(lambda (x) (memq x '(nil t unbased)))) (defcustom verilog-assignment-delay "" "Text used for delays in delayed assignments. Add a trailing space if set." @@ -1011,7 +1023,7 @@ the MSB or LSB of a signal inside an AUTORESET." (put 'verilog-assignment-delay 'safe-local-variable 'stringp) (defcustom verilog-auto-arg-sort nil - "If set, AUTOARG signal names will be sorted, not in declaration order. + "Non-nil means AUTOARG signal names will be sorted, not in declaration order. Declaration order is advantageous with order based instantiations and is the default for backward compatibility. Sorted order reduces changes when declarations are moved around in a file, and @@ -1023,7 +1035,7 @@ See also `verilog-auto-inst-sort'." (put 'verilog-auto-arg-sort 'safe-local-variable 'verilog-booleanp) (defcustom verilog-auto-inst-dot-name nil - "If true, when creating ports with AUTOINST, use .name syntax. + "Non-nil means when creating ports with AUTOINST, use .name syntax. This will use \".port\" instead of \".port(port)\" when possible. This is only legal in SystemVerilog files, and will confuse older simulators. Setting `verilog-auto-inst-vector' to nil may also @@ -1033,7 +1045,7 @@ be desirable to increase how often .name will be used." (put 'verilog-auto-inst-dot-name 'safe-local-variable 'verilog-booleanp) (defcustom verilog-auto-inst-param-value nil - "If set, AUTOINST will replace parameters with the parameter value. + "Non-nil means AUTOINST will replace parameters with the parameter value. If nil, leave parameters as symbolic names. Parameters must be in Verilog 2001 format #(...), and if a parameter is not @@ -1041,7 +1053,7 @@ listed as such there (as when the default value is acceptable), it will not be replaced, and will remain symbolic. For example, imagine a submodule uses parameters to declare the size of its -inputs. This is then used by a upper module: +inputs. This is then used by an upper module: module InstModule (o,i); parameter WIDTH; @@ -1070,20 +1082,20 @@ instead expand to: (put 'verilog-auto-inst-param-value 'safe-local-variable 'verilog-booleanp) (defcustom verilog-auto-inst-sort nil - "If set, AUTOINST signal names will be sorted, not in declaration order. + "Non-nil means AUTOINST signals will be sorted, not in declaration order. Also affects AUTOINSTPARAM. Declaration order is the default for backward compatibility, and as some teams prefer signals that are declared together to remain together. Sorted order reduces changes when declarations are moved around in a file. See also `verilog-auto-arg-sort'." - :version "24.1" + :version "24.1" ;; rev688 :group 'verilog-mode-auto :type 'boolean) (put 'verilog-auto-inst-sort 'safe-local-variable 'verilog-booleanp) (defcustom verilog-auto-inst-vector t - "If true, when creating default ports with AUTOINST, use bus subscripts. + "Non-nil means when creating default ports with AUTOINST, use bus subscripts. If nil, skip the subscript when it matches the entire bus as declared in the module (AUTOWIRE signals always are subscripted, you must manually declare the wire to have the subscripts removed.) Setting this to nil may @@ -1115,6 +1127,12 @@ won't merge conflict." :type 'integer) (put 'verilog-auto-inst-column 'safe-local-variable 'integerp) +(defcustom verilog-auto-inst-interfaced-ports t + "Non-nil means include interfaced ports in AUTOINST expansions." + :group 'verilog-mode-auto + :type 'boolean) +(put 'verilog-auto-inst-interfaced-ports 'safe-local-variable 'verilog-booleanp) + (defcustom verilog-auto-input-ignore-regexp nil "If set, when creating AUTOINPUT list, ignore signals matching this regexp. See the \\[verilog-faq] for examples on using this." @@ -1136,11 +1154,18 @@ See the \\[verilog-faq] for examples on using this." :type 'string) (put 'verilog-auto-output-ignore-regexp 'safe-local-variable 'stringp) +(defcustom verilog-auto-template-warn-unused nil + "Non-nil means report warning if an AUTO_TEMPLATE line is not used. +This feature is not supported before Emacs 21.1 or XEmacs 21.4." + :group 'verilog-mode-auto + :type 'boolean) +(put 'verilog-auto-template-warn-unused 'safe-local-variable 'verilog-booleanp) + (defcustom verilog-auto-tieoff-declaration "wire" - "Data type used for the declaration for AUTOTIEOFF. If \"wire\" then -create a wire, if \"assign\" create an assignment, else the data type for -variable creation." - :version "24.1" + "Data type used for the declaration for AUTOTIEOFF. +If \"wire\" then create a wire, if \"assign\" create an +assignment, else the data type for variable creation." + :version "24.1" ;; rev713 :group 'verilog-mode-auto :type 'string) (put 'verilog-auto-tieoff-declaration 'safe-local-variable 'stringp) @@ -1201,6 +1226,16 @@ For example, \"_t$\" matches typedefs named with _t, as in the C language." :group 'verilog-mode-auto :type 'hook) +(defcustom verilog-before-save-font-hook nil + "Hook run before `verilog-save-font-mods' removes highlighting." + :group 'verilog-mode-auto + :type 'hook) + +(defcustom verilog-after-save-font-hook nil + "Hook run after `verilog-save-font-mods' restores highlighting." + :group 'verilog-mode-auto + :type 'hook) + (defvar verilog-imenu-generic-expression '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4) ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3)) @@ -1430,6 +1465,8 @@ If set will become buffer local.") :help "Help on AUTOSENSE - sensitivity lists for always blocks"] ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff) :help "Help on AUTOTIEOFF - tying off unused outputs"] + ["AUTOUNDEF" (describe-function 'verilog-auto-undef) + :help "Help on AUTOUNDEF - undefine all local defines"] ["AUTOUNUSED" (describe-function 'verilog-auto-unused) :help "Help on AUTOUNUSED - terminating unused inputs"] ["AUTOWIRE" (describe-function 'verilog-auto-wire) @@ -1552,7 +1589,7 @@ If set will become buffer local.") FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace. The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\") will break, as the o's continuously replace. xa -> x works ok though." - ;; Hopefully soon to a emacs built-in + ;; Hopefully soon to an Emacs built-in ;; Also note \ in the replacement prevent multiple replacements; IE ;; (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil "wire@_@") ;; Gives "wire\([0-9]+\)_@" not "wire\([0-9]+\)_\([0-9]+\)" @@ -2401,7 +2438,6 @@ find the errors." "\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;28 "\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)" ;; - )) (defconst verilog-end-block-ordered-rry @@ -2629,11 +2665,11 @@ find the errors." "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass" )))) (defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>") -(defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?") +(defconst verilog-extended-case-re "\\(\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)") (defconst verilog-extended-complete-re - (concat "\\(\\\\s-+\\)?virtual\\s-+\\|\\\\|\\\\)" - "\\|\\(\\\\s-+\\)*\\(\\\\|\\\\|\\\\)" - "\\|\\(\\\\s-+\\)?\"DPI-C\"\\s-+\\(function\\>\\|task\\>\\)" + (concat "\\(\\(\\\\s-+\\)?virtual\\s-+\\|\\\\|\\\\)\\)" + "\\|\\(\\(\\\\s-+\\)*\\(\\\\|\\\\|\\\\)\\)" + "\\|\\(\\(\\\\s-+\\)?\\(\"DPI-C\"\\s-+\\)?\\(\\\\s-+\\)?\\(function\\>\\|task\\>\\)\\)" "\\|" verilog-extended-case-re )) (defconst verilog-basic-complete-re (eval-when-compile @@ -2645,9 +2681,7 @@ find the errors." )))) (defconst verilog-complete-reg (concat - verilog-extended-complete-re - "\\|" - verilog-basic-complete-re)) + verilog-extended-complete-re "\\|\\(" verilog-basic-complete-re "\\)")) (defconst verilog-end-statement-re (concat "\\(" verilog-beg-block-re "\\)\\|\\(" @@ -2764,7 +2798,8 @@ See also `verilog-font-lock-extra-types'.") (defvar verilog-font-lock-keywords-3 nil "Gaudy level highlighting for Verilog mode. See also `verilog-font-lock-extra-types'.") -(defvar verilog-font-lock-translate-off-face + +(defvar verilog-font-lock-translate-off-face 'verilog-font-lock-translate-off-face "Font to use for translated off regions.") (defface verilog-font-lock-translate-off-face @@ -2842,8 +2877,8 @@ See also `verilog-font-lock-extra-types'.") (verilog-pragma-keywords (eval-when-compile (verilog-regexp-opt - '("surefire" "synopsys" "rtl_synthesis" "verilint" "leda" "0in") nil - ))) + '("surefire" "auto" "synopsys" "rtl_synthesis" "verilint" "leda" "0in" + ) nil ))) (verilog-1800-2005-keywords (eval-when-compile @@ -2968,7 +3003,7 @@ See also `verilog-font-lock-extra-types'.") (append verilog-font-lock-keywords-1 (list ;; Fontify pragmas - (concat "\\(//\\s-*" verilog-pragma-keywords "\\s-.*\\)") + (concat "\\(//\\s-*\\(" verilog-pragma-keywords "\\)\\s-.*\\)") ;; Fontify escaped names '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face) ;; Fontify macro definitions/ uses @@ -3030,6 +3065,31 @@ For insignificant changes, see instead `verilog-save-buffer-state'." after-change-functions) (progn ,@body))) +(defvar verilog-save-font-mod-hooked nil + "Local variable when inside a `verilog-save-font-mods' block.") +(make-variable-buffer-local 'verilog-save-font-mod-hooked) + +(defmacro verilog-save-font-mods (&rest body) + "Execute BODY forms, disabling text modifications to allow performing BODY. +Includes temporary disabling of `font-lock' to restore the buffer +to full text form for parsing. Additional actions may be specified with +`verilog-before-save-font-hook' and `verilog-after-save-font-hook'." + ;; Before version 20, match-string with font-lock returns a + ;; vector that is not equal to the string. IE if on "input" + ;; nil==(equal "input" (progn (looking-at "input") (match-string 0))) + `(let* ((hooked (unless verilog-save-font-mod-hooked + (verilog-run-hooks 'verilog-before-save-font-hook) + t)) + (verilog-save-font-mod-hooked t) + (fontlocked (when (and (boundp 'font-lock-mode) font-lock-mode) + (font-lock-mode 0) + t))) + (unwind-protect + (progn ,@body) + ;; Unwind forms + (when fontlocked (font-lock-mode t)) + (when hooked (verilog-run-hooks 'verilog-after-save-font-hook))))) + ;; ;; Comment detection and caching @@ -3161,7 +3221,7 @@ to establish comment properties on all text." (defun verilog-insert (&rest stuff) "Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'. -Any insert that includes a comment must have the entire commente +Any insert that includes a comment must have the entire comment inserted using a single call to `verilog-insert'." (let ((pt (point))) (while stuff @@ -3565,9 +3625,10 @@ Key bindings specific to `verilog-mode-map' are: ;; Stuff for GNU Emacs (set (make-local-variable 'font-lock-defaults) - `((verilog-font-lock-keywords verilog-font-lock-keywords-1 - verilog-font-lock-keywords-2 - verilog-font-lock-keywords-3) + `((verilog-font-lock-keywords + verilog-font-lock-keywords-1 + verilog-font-lock-keywords-2 + verilog-font-lock-keywords-3) nil nil nil ,(if (functionp 'syntax-ppss) ;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses @@ -4049,7 +4110,7 @@ With ARG, first kill any existing labels." (if (looking-at verilog-label-re) (setq h (point)))) (goto-char h))) - ;; stop if we see a complete reg, perhaps an extended one + ;; stop if we see an extended complete reg, perhaps a complete one (and (looking-at verilog-complete-reg) (let* ((p (point))) @@ -4186,32 +4247,20 @@ More specifically, point @ in the line foo : @ begin" nil))) (defun verilog-backward-up-list (arg) - "Like `backward-up-list', but deal with comments." + "Call `backward-up-list' ARG, ignoring comments." (let ((parse-sexp-ignore-comments t)) (backward-up-list arg))) (defun verilog-forward-sexp-cmt (arg) - "Call `forward-sexp', inside comments." + "Call `forward-sexp' ARG, inside comments." (let ((parse-sexp-ignore-comments nil)) (forward-sexp arg))) (defun verilog-forward-sexp-ign-cmt (arg) - "Call `forward-sexp', ignoring comments." + "Call `forward-sexp' ARG, ignoring comments." (let ((parse-sexp-ignore-comments t)) (forward-sexp arg))) -(defun verilog-in-struct-region-p () - "Return true if in a struct region. -More specifically, in a list after a struct|union keyword." - (interactive) - (save-excursion - (let* ((state (verilog-syntax-ppss)) - (depth (nth 0 state))) - (if depth - (progn (verilog-backward-up-list depth) - (verilog-beg-of-statement) - (looking-at "\\?\\s-*\\")))))) - (defun verilog-in-generate-region-p () "Return true if in a generate region. More specifically, after a generate and before an endgenerate." @@ -4658,10 +4707,10 @@ primitive or interface named NAME." (cond ((match-end 5) ;; of verilog-end-block-ordered-re (setq reg "\\(\\\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)") - (setq name-re "\\w+\\s-*(") - ) + (setq name-re "\\w+\\s-*(")) ((match-end 6) ;; of verilog-end-block-ordered-re - (setq reg "\\(\\\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")) + (setq reg "\\(\\\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)") + (setq name-re "\\w+\\s-*(")) ((match-end 7) ;; of verilog-end-block-ordered-re (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\")) ((match-end 8) ;; of verilog-end-block-ordered-re @@ -4977,25 +5026,24 @@ becomes: (compile compile-command)) (defun verilog-preprocess (&optional command filename) - "Preprocess the buffer, similar to `compile', but leave output in Verilog-Mode. + "Preprocess the buffer, similar to `compile', but put output in Verilog-Mode. Takes optional COMMAND or defaults to `verilog-preprocessor', and -FILENAME or defaults to `buffer-file-name`." +FILENAME to find directory to run in, or defaults to `buffer-file-name`." (interactive (list (let ((default (verilog-expand-command verilog-preprocessor))) (set (make-local-variable `verilog-preprocessor) - (read-from-minibuffer "Run Preprocessor (like this): " - default nil nil - 'verilog-preprocess-history default))))) + (read-from-minibuffer "Run Preprocessor (like this): " + default nil nil + 'verilog-preprocess-history default))))) (unless command (setq command (verilog-expand-command verilog-preprocessor))) (let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode)) - (dir (file-name-directory (or filename buffer-file-name))) - (file (file-name-nondirectory (or filename buffer-file-name))) - (cmd (concat "cd " dir "; " command " " file))) + (dir (file-name-directory (or filename buffer-file-name))) + (cmd (concat "cd " dir "; " command))) (with-output-to-temp-buffer "*Verilog-Preprocessed*" (with-current-buffer (get-buffer "*Verilog-Preprocessed*") (insert (concat "// " cmd "\n")) - (shell-command cmd "*Verilog-Preprocessed*") + (call-process shell-file-name nil t nil shell-command-switch cmd) (verilog-mode) ;; Without this force, it takes a few idle seconds ;; to get the color, which is very jarring @@ -5006,17 +5054,30 @@ FILENAME or defaults to `buffer-file-name`." ;; Batch ;; +(defun verilog-warn (string &rest args) + "Print a warning with `format' using STRING and optional ARGS." + (apply 'message (concat "%%Warning: " string) args)) + +(defun verilog-warn-error (string &rest args) + "Call `error' using STRING and optional ARGS. +If `verilog-warn-fatal' is non-nil, call `verilog-warn' instead." + (if verilog-warn-fatal + (apply 'error string args) + (apply 'verilog-warn string args))) + (defmacro verilog-batch-error-wrapper (&rest body) "Execute BODY and add error prefix to any errors found. This lets programs calling batch mode to easily extract error messages." - `(condition-case err - (progn ,@body) - (error - (error "%%Error: %s%s" (error-message-string err) - (if (featurep 'xemacs) "\n" ""))))) ;; XEmacs forgets to add a newline + `(let ((verilog-warn-fatal nil)) + (condition-case err + (progn ,@body) + (error + (error "%%Error: %s%s" (error-message-string err) + (if (featurep 'xemacs) "\n" "")))))) ;; XEmacs forgets to add a newline (defun verilog-batch-execute-func (funref &optional no-save) - "Internal processing of a batch command, running FUNREF on all command arguments. + "Internal processing of a batch command. +Runs FUNREF on all command arguments. Save the result unless optional NO-SAVE is t." (verilog-batch-error-wrapper ;; Setting global variables like that is *VERY NASTY* !!! --Stef @@ -5088,7 +5149,7 @@ line in bottom-up order." (verilog-batch-execute-func `verilog-inject-auto)) (defun verilog-batch-indent () - "For use with --batch, reindent an a entire file as a stand-alone tool. + "For use with --batch, reindent an entire file as a stand-alone tool. This sets up the appropriate Verilog mode environment, calls \\[verilog-indent-buffer] on all command-line files, and saves the buffers." (unless noninteractive @@ -5219,7 +5280,7 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)." (verilog-beg-of-statement) ;; doesn't get to beginning (if (looking-at verilog-property-re) (throw 'nesting 'statement) ; We don't need an endproperty for these - (throw 'nesting 'block) ;We still need a endproperty + (throw 'nesting 'block) ;We still need an endproperty )) (t ; endblock ; try to leap back to matching outward block by striding across @@ -5312,7 +5373,6 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)." (t (setq depth (verilog-current-indent-level))))) (message "You are at nesting %s depth %d" type depth)))) - (defun verilog-calc-1 () (catch 'nesting (let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)"))) @@ -5370,9 +5430,10 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)." ; endfunction (verilog-beg-of-statement) (if (looking-at verilog-beg-block-re-ordered) - (throw 'nesting 'block) - (throw 'nesting 'defun))) + (throw 'nesting 'block) + (throw 'nesting 'defun))) + ;; ((looking-at "\\") ; *sigh* ; {assert|assume|cover} property (); are complete @@ -5382,7 +5443,7 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)." (verilog-beg-of-statement) (if (looking-at verilog-property-re) (throw 'continue 'statement) ; We don't need an endproperty for these - (throw 'nesting 'block) ;We still need a endproperty + (throw 'nesting 'block) ;We still need an endproperty )) (t (throw 'nesting 'block)))) @@ -5715,7 +5776,7 @@ Set point to where line starts." (forward-comment (- (buffer-size)))) (defun verilog-backward-syntactic-ws-quick () - "As with `verilog-backward-syntactic-ws' but uses `verilog-scan' cache." + "As with `verilog-backward-syntactic-ws' but use `verilog-scan' cache." (while (cond ((bobp) nil) ; Done ((> (skip-syntax-backward " ") 0) @@ -5864,7 +5925,7 @@ May cache result using `verilog-syntax-ppss'." (defun verilog-in-paren-quick () "Return true if in a parenthetical expression. -Always starts from point-min, to allow inserts with hooks disabled." +Always starts from `point-min', to allow inserts with hooks disabled." ;; The -quick refers to its use alongside the other -quick functions, ;; not that it's likely to be faster than verilog-in-paren. (let ((state (save-excursion (parse-partial-sexp (point-min) (point))))) @@ -6118,7 +6179,7 @@ Only look at a few lines to determine indent level." (indent-line-to val) (if (and (not verilog-indent-lists) (verilog-in-paren)) - (verilog-pretty-declarations)) + (verilog-pretty-declarations-auto)) )) ((= (preceding-char) ?\) ) (goto-char here) @@ -6154,7 +6215,7 @@ Only look at a few lines to determine indent level." (looking-at verilog-declaration-re)))) (indent-line-to val) (if decl - (verilog-pretty-declarations)))) + (verilog-pretty-declarations-auto)))) (;-- Handle the ends (or @@ -6285,6 +6346,12 @@ ARG is ignored, for `comment-indent-function' compatibility." ;; +(defun verilog-pretty-declarations-auto (&optional quiet) + "Call `verilog-pretty-declarations' QUIET based on `verilog-auto-lineup'." + (when (or (eq 'all verilog-auto-lineup) + (eq 'declarations verilog-auto-lineup)) + (verilog-pretty-declarations quiet))) + (defun verilog-pretty-declarations (&optional quiet) "Line up declarations around point. Be verbose about progress unless optional QUIET set." @@ -6431,100 +6498,101 @@ Be verbose about progress unless optional QUIET set." (interactive) (if (not (verilog-in-comment-or-string-p)) (save-excursion - (let ((rexp (concat "^\\s-*" verilog-complete-reg))) - (beginning-of-line) - (if (and (not (looking-at rexp )) - (looking-at verilog-assignment-operation-re) - (save-excursion - (goto-char (match-end 2)) - (and (not (verilog-in-attribute-p)) - (not (verilog-in-parameter-p)) - (not (verilog-in-comment-or-string-p))))) - (let* ((here (point)) - (e) (r) - (start - (progn - (beginning-of-line) - (setq e (point)) - (verilog-backward-syntactic-ws) - (beginning-of-line) - (while (and (not (looking-at rexp )) - (looking-at verilog-assignment-operation-re) - (not (bobp)) - ) - (setq e (point)) - (verilog-backward-syntactic-ws) - (beginning-of-line) - ) ;Ack, need to grok `define - e)) - (end - (progn - (goto-char here) - (end-of-line) - (setq e (point)) ;Might be on last line - (verilog-forward-syntactic-ws) - (beginning-of-line) - (while (and - (not (looking-at rexp )) - (looking-at verilog-assignment-operation-re) - (progn - (end-of-line) - (not (eq e (point))))) - (setq e (point)) - (verilog-forward-syntactic-ws) - (beginning-of-line) - ) - e)) - (endpos (set-marker (make-marker) end)) - (ind) - ) - (goto-char start) - (verilog-do-indent (verilog-calculate-indent)) - (if (and (not quiet) - (> (- end start) 100)) - (message "Lining up expressions..(please stand by)")) - - ;; Set indent to minimum throughout region - (while (< (point) (marker-position endpos)) - (beginning-of-line) - (verilog-just-one-space verilog-assignment-operation-re) - (beginning-of-line) - (verilog-do-indent (verilog-calculate-indent)) - (end-of-line) - (verilog-forward-syntactic-ws) - ) - - ;; Now find biggest prefix - (setq ind (verilog-get-lineup-indent-2 verilog-assignment-operation-re start endpos)) - - ;; Now indent each line. - (goto-char start) - (while (progn (setq e (marker-position endpos)) - (setq r (- e (point))) - (> r 0)) - (setq e (point)) - (if (not quiet) (message "%d" r)) - (cond - ((looking-at verilog-assignment-operation-re) - (goto-char (match-beginning 2)) - (if (not (or (verilog-in-parenthesis-p) ;; leave attributes and comparisons alone - (verilog-in-coverage-p))) - (if (eq (char-after) ?=) - (indent-to (1+ ind)) ; line up the = of the <= with surrounding = - (indent-to ind) - )) - ) - ((verilog-continued-line-1 start) - (goto-char e) - (indent-line-to ind)) - (t ; Must be comment or white space - (goto-char e) - (verilog-forward-ws&directives) - (forward-line -1)) - ) - (forward-line 1)) - (unless quiet (message "")) - )))))) + (let ( (rexp (concat "^\\s-*" verilog-complete-reg)) + (rexp1 (concat "^\\s-*" verilog-basic-complete-re))) + (beginning-of-line) + (if (and (not (looking-at rexp )) + (looking-at verilog-assignment-operation-re) + (save-excursion + (goto-char (match-end 2)) + (and (not (verilog-in-attribute-p)) + (not (verilog-in-parameter-p)) + (not (verilog-in-comment-or-string-p))))) + (let* ((here (point)) + (e) (r) + (start + (progn + (beginning-of-line) + (setq e (point)) + (verilog-backward-syntactic-ws) + (beginning-of-line) + (while (and (not (looking-at rexp1)) + (looking-at verilog-assignment-operation-re) + (not (bobp)) + ) + (setq e (point)) + (verilog-backward-syntactic-ws) + (beginning-of-line) + ) ;Ack, need to grok `define + e)) + (end + (progn + (goto-char here) + (end-of-line) + (setq e (point)) ;Might be on last line + (verilog-forward-syntactic-ws) + (beginning-of-line) + (while (and + (not (looking-at rexp1 )) + (looking-at verilog-assignment-operation-re) + (progn + (end-of-line) + (not (eq e (point))))) + (setq e (point)) + (verilog-forward-syntactic-ws) + (beginning-of-line) + ) + e)) + (endpos (set-marker (make-marker) end)) + (ind) + ) + (goto-char start) + (verilog-do-indent (verilog-calculate-indent)) + (if (and (not quiet) + (> (- end start) 100)) + (message "Lining up expressions..(please stand by)")) + + ;; Set indent to minimum throughout region + (while (< (point) (marker-position endpos)) + (beginning-of-line) + (verilog-just-one-space verilog-assignment-operation-re) + (beginning-of-line) + (verilog-do-indent (verilog-calculate-indent)) + (end-of-line) + (verilog-forward-syntactic-ws) + ) + + ;; Now find biggest prefix + (setq ind (verilog-get-lineup-indent-2 verilog-assignment-operation-re start endpos)) + + ;; Now indent each line. + (goto-char start) + (while (progn (setq e (marker-position endpos)) + (setq r (- e (point))) + (> r 0)) + (setq e (point)) + (if (not quiet) (message "%d" r)) + (cond + ((looking-at verilog-assignment-operation-re) + (goto-char (match-beginning 2)) + (if (not (or (verilog-in-parenthesis-p) ;; leave attributes and comparisons alone + (verilog-in-coverage-p))) + (if (eq (char-after) ?=) + (indent-to (1+ ind)) ; line up the = of the <= with surrounding = + (indent-to ind) + )) + ) + ((verilog-continued-line-1 start) + (goto-char e) + (indent-line-to ind)) + (t ; Must be comment or white space + (goto-char e) + (verilog-forward-ws&directives) + (forward-line -1)) + ) + (forward-line 1)) + (unless quiet (message "")) + )))))) (defun verilog-just-one-space (myre) "Remove extra spaces around regular expression MYRE." @@ -7365,6 +7433,7 @@ See also `verilog-sk-header' for an alternative format." ;; ;; Elements of a signal list +;; Unfortunately we use 'assoc' on this, so can't be a vector (defsubst verilog-sig-new (name bits comment mem enum signed type multidim modport) (list name bits comment mem enum signed type multidim modport)) (defsubst verilog-sig-name (sig) @@ -7381,6 +7450,8 @@ See also `verilog-sk-header' for an alternative format." (nth 5 sig)) (defsubst verilog-sig-type (sig) (nth 6 sig)) +(defsubst verilog-sig-type-set (sig type) + (setcar (nthcdr 6 sig) type)) (defsubst verilog-sig-multidim (sig) (nth 7 sig)) (defsubst verilog-sig-multidim-string (sig) @@ -7396,17 +7467,17 @@ See also `verilog-sk-header' for an alternative format." (verilog-make-width-expression (verilog-sig-bits sig))) (defsubst verilog-alw-new (outputs-del outputs-imm temps inputs) - (list outputs-del outputs-imm temps inputs)) + (vector outputs-del outputs-imm temps inputs)) (defsubst verilog-alw-get-outputs-delayed (sigs) - (nth 0 sigs)) + (aref sigs 0)) (defsubst verilog-alw-get-outputs-immediate (sigs) - (nth 1 sigs)) + (aref sigs 1)) (defsubst verilog-alw-get-temps (sigs) - (nth 2 sigs)) + (aref sigs 2)) (defsubst verilog-alw-get-inputs (sigs) - (nth 3 sigs)) + (aref sigs 3)) (defsubst verilog-alw-get-uses-delayed (sigs) - (nth 0 sigs)) + (aref sigs 0)) (defsubst verilog-modi-new (name fob pt type) (vector name fob pt type)) @@ -7459,6 +7530,11 @@ See also `verilog-sk-header' for an alternative format." (defsubst verilog-subdecls-get-interfaced (subdecls) (aref subdecls 4)) +(defun verilog-signals-from-signame (signame-list) + "Return signals in standard form from SIGNAME-LIST, a simple list of names." + (mapcar (lambda (name) (verilog-sig-new name nil nil nil nil nil nil nil nil)) + signame-list)) + (defun verilog-signals-not-in (in-list not-list) "Return list of signals in IN-LIST that aren't also in NOT-LIST. Also remove any duplicates in IN-LIST. @@ -7471,17 +7547,17 @@ Signals must be in standard (base vector) form." (puthash (car (car not-list)) t ht) (setq not-list (cdr not-list))) (while in-list - (when (not (gethash (car (car in-list)) ht)) + (when (not (gethash (verilog-sig-name (car in-list)) ht)) (setq out-list (cons (car in-list) out-list)) - (puthash (car (car in-list)) t ht)) + (puthash (verilog-sig-name (car in-list)) t ht)) (setq in-list (cdr in-list))) (nreverse out-list))) ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4) (t (let (out-list) (while in-list - (if (not (or (assoc (car (car in-list)) not-list) - (assoc (car (car in-list)) out-list))) + (if (not (or (assoc (verilog-sig-name (car in-list)) not-list) + (assoc (verilog-sig-name (car in-list)) out-list))) (setq out-list (cons (car in-list) out-list))) (setq in-list (cdr in-list))) (nreverse out-list))))) @@ -7499,13 +7575,22 @@ Signals must be in standard (base vector) form." (defun verilog-signals-sort-compare (a b) "Compare signal A and B for sorting." - (string< (car a) (car b))) + (string< (verilog-sig-name a) (verilog-sig-name b))) (defun verilog-signals-not-params (in-list) "Return list of signals in IN-LIST that aren't parameters or numeric constants." (let (out-list) (while in-list - (unless (boundp (intern (concat "vh-" (car (car in-list))))) + (unless (boundp (intern (concat "vh-" (verilog-sig-name (car in-list))))) + (setq out-list (cons (car in-list) out-list))) + (setq in-list (cdr in-list))) + (nreverse out-list))) + +(defun verilog-signals-with (func in-list) + "Return IN-LIST with only signals where FUNC passed each signal is true." + (let (out-list) + (while in-list + (when (funcall func (car in-list)) (setq out-list (cons (car in-list) out-list))) (setq in-list (cdr in-list))) (nreverse out-list))) @@ -7594,20 +7679,67 @@ Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]." ;; out-list)) -(defun verilog-sig-tieoff (sig &optional no-width) +(defun verilog-sig-tieoff (sig) "Return tieoff expression for given SIG, with appropriate width. -Ignore width if optional NO-WIDTH is set." - (let* ((width (if no-width nil (verilog-sig-width sig)))) - (concat - (if (and verilog-active-low-regexp - (string-match verilog-active-low-regexp (verilog-sig-name sig))) - "~" "") - (cond ((not width) - "0") - ((string-match "^[0-9]+$" width) - (concat width (if (verilog-sig-signed sig) "'sh0" "'h0"))) - (t - (concat "{" width "{1'b0}}")))))) +Tieoff value uses `verilog-active-low-regexp' and +`verilog-auto-reset-widths'." + (concat + (if (and verilog-active-low-regexp + (string-match verilog-active-low-regexp (verilog-sig-name sig))) + "~" "") + (cond ((not verilog-auto-reset-widths) + "0") + ((equal verilog-auto-reset-widths 'unbased) + "'0") + ;; Else presume verilog-auto-reset-widths is true + (t + (let* ((width (verilog-sig-width sig))) + (if (string-match "^[0-9]+$" width) + (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")) + (concat "{" width "{1'b0}}"))))))) + +;; +;; Dumping +;; + +(defun verilog-decls-princ (decls) + "For debug, dump the `verilog-read-decls' structure DECLS." + (verilog-signals-princ (verilog-decls-get-outputs decls) + "Outputs:\n" " ") + (verilog-signals-princ (verilog-decls-get-inouts decls) + "Inout:\n" " ") + (verilog-signals-princ (verilog-decls-get-inputs decls) + "Inputs:\n" " ") + (verilog-signals-princ (verilog-decls-get-vars decls) + "Vars:\n" " ") + (verilog-signals-princ (verilog-decls-get-assigns decls) + "Assigns:\n" " ") + (verilog-signals-princ (verilog-decls-get-consts decls) + "Consts:\n" " ") + (verilog-signals-princ (verilog-decls-get-gparams decls) + "Gparams:\n" " ") + (verilog-signals-princ (verilog-decls-get-interfaces decls) + "Interfaces:\n" " ") + (princ "\n")) + +(defun verilog-signals-princ (signals &optional header prefix) + "For debug, dump internal SIGNALS structures, with HEADER and PREFIX." + (when signals + (princ header) + (while signals + (let ((sig (car signals))) + (setq signals (cdr signals)) + (princ prefix) + (princ "\"") (princ (verilog-sig-name sig)) (princ "\"") + (princ " bits=") (princ (verilog-sig-bits sig)) + (princ " cmt=") (princ (verilog-sig-comment sig)) + (princ " mem=") (princ (verilog-sig-memory sig)) + (princ " enum=") (princ (verilog-sig-enum sig)) + (princ " sign=") (princ (verilog-sig-signed sig)) + (princ " type=") (princ (verilog-sig-type sig)) + (princ " dim=") (princ (verilog-sig-multidim sig)) + (princ " modp=") (princ (verilog-sig-modport sig)) + (princ "\n"))))) ;; ;; Port/Wire/Etc Reading @@ -7701,7 +7833,7 @@ Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters." (let ((olist)) (save-excursion ;; /*AUTOPUNT("parameter", "parameter")*/ - (search-backward "(") + (backward-sexp 1) (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?") (setq olist (cons (match-string 1) olist)) (goto-char (match-end 0)))) @@ -7716,10 +7848,10 @@ Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters." (defun verilog-read-decls () "Compute signal declaration information for the current module at point. -Return a array of [outputs inouts inputs wire reg assign const]." +Return an array of [outputs inouts inputs wire reg assign const]." (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max))) (functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t) - in-modport ign-prop + in-modport ptype ign-prop sigs-in sigs-out sigs-inout sigs-var sigs-assign sigs-const sigs-gparam sigs-intf vec expect-signal keywd newsig rvalue enum io signed typedefed multidim @@ -7731,13 +7863,13 @@ Return a array of [outputs inouts inputs wire reg assign const]." ;;(if dbg (setq dbg (concat dbg (format "Pt %s Vec %s C%c Kwd'%s'\n" (point) vec (following-char) keywd)))) (cond ((looking-at "//") - (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") - (setq enum (match-string 1))) + (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") + (setq enum (match-string 2))) (search-forward "\n")) ((looking-at "/\\*") (forward-char 2) - (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") - (setq enum (match-string 1))) + (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") + (setq enum (match-string 2))) (or (search-forward "*/") (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point)))) ((looking-at "(\\*") @@ -7795,33 +7927,49 @@ Return a array of [outputs inouts inputs wire reg assign const]." (when (string-match "^\\\\" (match-string 1)) (setq keywd (concat keywd " ")))) ;; Escaped ID needs space at end (cond ((equal keywd "input") - (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren - expect-signal 'sigs-in io t modport nil)) + (setq vec nil enum nil rvalue nil newsig nil signed nil + typedefed nil multidim nil ptype nil modport nil + expect-signal 'sigs-in io t sig-paren paren)) ((equal keywd "output") - (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren - expect-signal 'sigs-out io t modport nil)) + (setq vec nil enum nil rvalue nil newsig nil signed nil + typedefed nil multidim nil ptype nil modport nil + expect-signal 'sigs-out io t sig-paren paren)) ((equal keywd "inout") - (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren - expect-signal 'sigs-inout io t modport nil)) + (setq vec nil enum nil rvalue nil newsig nil signed nil + typedefed nil multidim nil ptype nil modport nil + expect-signal 'sigs-inout io t sig-paren paren)) ((equal keywd "parameter") - (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren - expect-signal 'sigs-gparam io t modport nil)) - ((member keywd '("wire" - "tri" "tri0" "tri1" "triand" "trior" "wand" "wor" - "reg" "trireg" + (setq vec nil enum nil rvalue nil signed nil + typedefed nil multidim nil ptype nil modport nil + expect-signal 'sigs-gparam io t sig-paren paren)) + ((member keywd '("wire" "reg" ; Fast + ;; net_type + "tri" "tri0" "tri1" "triand" "trior" "trireg" + "uwire" "wand" "wor" + ;; integer_atom_type "byte" "shortint" "int" "longint" "integer" "time" + "supply0" "supply1" + ;; integer_vector_type - "reg" above "bit" "logic" + ;; non_integer_type "shortreal" "real" "realtime" + ;; data_type "string" "event" "chandle")) - (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren - expect-signal 'sigs-var modport nil))) + (cond (io + (setq typedefed + (if typedefed (concat typedefed " " keywd) keywd))) + (t (setq vec nil enum nil rvalue nil signed nil + typedefed nil multidim nil sig-paren paren + expect-signal 'sigs-var modport nil)))) ((equal keywd "assign") - (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren - expect-signal 'sigs-assign modport nil)) - ((member keywd '("supply0" "supply1" "supply" - "localparam" "genvar")) - (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren - expect-signal 'sigs-const modport nil))) + (setq vec nil enum nil rvalue nil signed nil + typedefed nil multidim nil ptype nil modport nil + expect-signal 'sigs-assign sig-paren paren)) + ((member keywd '("localparam" "genvar")) + (unless io + (setq vec nil enum nil rvalue nil signed nil + typedefed nil multidim nil ptype nil modport nil + expect-signal 'sigs-const sig-paren paren))) ((member keywd '("signed" "unsigned")) (setq signed keywd)) ((member keywd '("assert" "assume" "cover" "expect" "restrict")) @@ -7835,11 +7983,14 @@ Return a array of [outputs inouts inputs wire reg assign const]." (setq functask (1- functask))) ((equal keywd "modport") (setq in-modport t)) + ((equal keywd "type") + (setq ptype t)) ;; Ifdef? Ignore name of define ((member keywd '("`ifdef" "`ifndef" "`elsif")) (setq rvalue t)) ;; Type? - ((verilog-typedef-name-p keywd) + ((unless ptype + (verilog-typedef-name-p keywd)) (setq typedefed keywd)) ;; Interface with optional modport in v2k arglist? ;; Skip over parsing modport, and take the interface name as the type @@ -7848,8 +7999,10 @@ Return a array of [outputs inouts inputs wire reg assign const]." (not rvalue) (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*")) (when (match-end 2) (goto-char (match-end 2))) - (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed keywd multidim nil sig-paren paren - expect-signal 'sigs-intf io t modport (match-string 2))) + (setq vec nil enum nil rvalue nil signed nil + typedefed keywd multidim nil ptype nil modport (match-string 2) + newsig nil sig-paren paren + expect-signal 'sigs-intf io t )) ;; Ignore dotted LHS assignments: "assign foo.bar = z;" ((looking-at "\\s-*\\.") (goto-char (match-end 0)) @@ -7888,7 +8041,7 @@ Return a array of [outputs inouts inputs wire reg assign const]." (eval-when-compile ;; Prevent compile warnings; these are let's, not globals ;; Do not remove the eval-when-compile - ;; - we want a error when we are debugging this code if they are refed. + ;; - we want an error when we are debugging this code if they are refed. (defvar sigs-in) (defvar sigs-inout) (defvar sigs-out) @@ -7918,7 +8071,8 @@ Return a array of [outputs inouts inputs wire reg assign const]." (verilog-sig-memory portdata) nil (verilog-sig-signed portdata) - (verilog-sig-type portdata) + (unless (member (verilog-sig-type portdata) '("wire" "reg")) + (verilog-sig-type portdata)) multidim nil) sigs-inout))) ((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls))) @@ -7931,7 +8085,13 @@ Return a array of [outputs inouts inputs wire reg assign const]." (verilog-sig-memory portdata) nil (verilog-sig-signed portdata) - (verilog-sig-type portdata) + ;; Though ok in SV, in V2K code, propagating the + ;; "reg" in "output reg" upwards isn't legal. + ;; Also for backwards compatibility we don't propagate + ;; "input wire" upwards. + ;; See also `verilog-signals-edit-wire-reg'. + (unless (member (verilog-sig-type portdata) '("wire" "reg")) + (verilog-sig-type portdata)) multidim nil) sigs-out))) ((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls))) @@ -7944,7 +8104,8 @@ Return a array of [outputs inouts inputs wire reg assign const]." (verilog-sig-memory portdata) nil (verilog-sig-signed portdata) - (verilog-sig-type portdata) + (unless (member (verilog-sig-type portdata) '("wire" "reg")) + (verilog-sig-type portdata)) multidim nil) sigs-in))) ((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls))) @@ -8110,9 +8271,9 @@ Inserts the list of signals found." (defun verilog-read-sub-decls () "Internally parse signals going to modules under this module. -Return a array of [ outputs inouts inputs ] signals for modules that are +Return an array of [ outputs inouts inputs ] signals for modules that are instantiated in this module. For example if declare A A (.B(SIG)) and SIG -is a output, then SIG will be included in the list. +is an output, then SIG will be included in the list. This only works on instantiations created with /*AUTOINST*/ converted by \\[verilog-auto-inst]. Otherwise, it would have to read in the whole @@ -8245,7 +8406,7 @@ For example if declare A A (.B(SIG)) then B will be included in the list." (setq verilog-cache-has-lisp (re-search-forward "\\" end-pt t) + (goto-char (point-min))) + (while (verilog-re-search-forward-quick + "`\\(define\\|undef\\)\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" end-pt t) + (cond ((equal (match-string-no-properties 1) "define") + (setq def (match-string-no-properties 2)) + (when (and (or (not regexp) + (string-match regexp def)) + (not (member def defs))) ;; delete-dups not in 21.1 + (setq defs (cons def defs)))) + (t + (setq defs (delete (match-string-no-properties 2) defs)))))) + ;; Insert + (setq defs (sort defs 'string<)) + (when defs + (forward-line 1) + (verilog-insert-indent "// Beginning of automatic undefs\n") + (while defs + (verilog-insert-indent "`undef " (car defs) "\n") + (setq defs (cdr defs))) + (verilog-insert-indent "// End of automatics\n"))))) + (defun verilog-auto-unused () "Expand AUTOUNUSED statements, as part of \\[verilog-auto]. Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused @@ -11981,17 +12256,17 @@ Remove user provided prefix ELIM-REGEXP." (defun verilog-auto-ascii-enum () "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto]. -Create a register to contain the ASCII decode of a enumerated signal type. +Create a register to contain the ASCII decode of an enumerated signal type. This will allow trace viewers to show the ASCII name of states. -First, parameters are built into a enumeration using the synopsys enum +First, parameters are built into an enumeration using the synopsys enum comment. The comment must be between the keyword and the symbol. \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.) Next, registers which that enum applies to are also tagged with the same enum. -Finally, a AUTOASCIIENUM command is used. +Finally, an AUTOASCIIENUM command is used. The first parameter is the name of the signal to be decoded. @@ -12001,17 +12276,19 @@ Finally, a AUTOASCIIENUM command is used. tell viewers like Dinotrace to display in ASCII format. The third optional parameter is a string which will be removed - from the state names. It defaults to "" which removes nothing. + from the state names. It defaults to \"\" which removes nothing. The fourth optional parameter is \"onehot\" to force one-hot - decoding. If unspecified, if and only if the first parameter + decoding. If unspecified, if and only if the first parameter width is 2^(number of states in enum) and does NOT match the - width of the enum, the signal is assumed to be a one hot + width of the enum, the signal is assumed to be a one-hot decode. Otherwise, it's a normal encoded state vector. `verilog-auto-wire-type' may be used to change the datatype of the declarations. + \"auto enum\" may be used in place of \"synopsys enum\". + An example: //== State enumeration @@ -12066,7 +12343,7 @@ Typing \\[verilog-auto] will make this into: (undecode-sig (or (assoc undecode-name sig-list-all) (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name))) (undecode-enum (or (verilog-sig-enum undecode-sig) - (error "%s: Signal %s does not have a enum tag" (verilog-point-text) undecode-name))) + (error "%s: Signal %s does not have an enum tag" (verilog-point-text) undecode-name))) ;; (enum-sigs (verilog-signals-not-in (or (verilog-signals-matching-enum sig-list-consts undecode-enum) @@ -12159,12 +12436,39 @@ being different from the final output's line numbering." (string-to-number (match-string 2))))) t t)))) +(defun verilog-auto-template-lint () + "Check AUTO_TEMPLATEs for unused lines. +Enable with `verilog-auto-template-warn-unused'." + (let ((name1 (or (buffer-file-name) (buffer-name)))) + (save-excursion + (goto-char (point-min)) + (while (re-search-forward + "^\\s-*/?\\*?\\s-*[a-zA-Z0-9`_$]+\\s-+AUTO_TEMPLATE" nil t) + (let* ((tpl-info (verilog-read-auto-template-middle)) + (tpl-list (aref tpl-info 1)) + (tlines (append (nth 0 tpl-list) (nth 1 tpl-list))) + tpl-ass) + (while tlines + (setq tpl-ass (car tlines) + tlines (cdr tlines)) + ;;; + (unless (or (not (eval-when-compile (fboundp 'make-hash-table))) ;; Not supported, no warning + (not verilog-auto-template-hits) + (gethash (vector (nth 2 tpl-ass) (nth 3 tpl-ass)) + verilog-auto-template-hits)) + (verilog-warn-error "%s:%d: AUTO_TEMPLATE line unused: \".%s (%s)\"" + name1 + (+ (elt tpl-ass 3) ;; Template line number + (count-lines (point-min) (point))) + (elt tpl-ass 0) (elt tpl-ass 1)) + ))))))) + ;; ;; Auto top level ;; -(defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing a arg +(defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing an arg "Expand AUTO statements. Look for any /*AUTO...*/ commands in the code, as used in instantiations or argument headers. Update the list of signals @@ -12219,6 +12523,7 @@ Using \\[describe-function], see also: `verilog-auto-reset' for AUTORESET flop resets `verilog-auto-sense' for AUTOSENSE always sensitivity lists `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs + `verilog-auto-undef' for AUTOUNDEF `undef of local `defines `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts `verilog-auto-wire' for AUTOWIRE instantiation wires @@ -12232,21 +12537,15 @@ Wilson Snyder (wsnyder@wsnyder.org)." (unless noninteractive (message "Updating AUTOs...")) (if (fboundp 'dinotrace-unannotate-all) (dinotrace-unannotate-all)) - (let ((oldbuf (if (not (buffer-modified-p)) - (buffer-string))) - ;; Before version 20, match-string with font-lock returns a - ;; vector that is not equal to the string. IE if on "input" - ;; nil==(equal "input" (progn (looking-at "input") (match-string 0))) - (fontlocked (when (and (boundp 'font-lock-mode) - font-lock-mode) - (font-lock-mode 0) - t)) - ;; Cache directories; we don't write new files, so can't change - (verilog-dir-cache-preserving t) - ;; Cache current module - (verilog-modi-cache-current-enable t) - (verilog-modi-cache-current-max (point-min)) ; IE it's invalid - verilog-modi-cache-current) + (verilog-save-font-mods + (let ((oldbuf (if (not (buffer-modified-p)) + (buffer-string))) + ;; Cache directories; we don't write new files, so can't change + (verilog-dir-cache-preserving t) + ;; Cache current module + (verilog-modi-cache-current-enable t) + (verilog-modi-cache-current-max (point-min)) ; IE it's invalid + verilog-modi-cache-current) (unwind-protect ;; Disable change hooks for speed ;; This let can't be part of above let; must restore @@ -12257,6 +12556,8 @@ Wilson Snyder (wsnyder@wsnyder.org)." ;; Wipe cache; otherwise if we AUTOed a block above this one, ;; we'll misremember we have generated IOs, confusing AUTOOUTPUT (setq verilog-modi-cache-list nil) + ;; Local state + (setq verilog-auto-template-hits nil) ;; If we're not in verilog-mode, change syntax table so parsing works right (unless (eq major-mode `verilog-mode) (verilog-mode)) ;; Allow user to customize @@ -12272,6 +12573,8 @@ Wilson Snyder (wsnyder@wsnyder.org)." (when verilog-auto-read-includes (verilog-read-includes) (verilog-read-defines nil nil t)) + ;; Setup variables due to SystemVerilog expansion + (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic-setup) ;; This particular ordering is important ;; INST: Lower modules correct, no internal dependencies, FIRST (verilog-preserve-modi-cache @@ -12284,7 +12587,7 @@ Wilson Snyder (wsnyder@wsnyder.org)." (verilog-inject-arg)) ;; ;; Do user inserts first, so their code can insert AUTOs - ;; We may provide a AUTOINSERTLISPLAST if another cleanup pass is needed + ;; We may provide an AUTOINSERTLISPLAST if another cleanup pass is needed (verilog-auto-re-search-do "/\\*AUTOINSERTLISP(.*?)\\*/" 'verilog-auto-insert-lisp) ;; Expand instances before need the signals the instances input/output @@ -12313,6 +12616,8 @@ Wilson Snyder (wsnyder@wsnyder.org)." (verilog-auto-re-search-do "/\\*AUTOINOUT\\*/" 'verilog-auto-inout) ;; Then tie off those in/outs (verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/" 'verilog-auto-tieoff) + ;; These can be anywhere after AUTOINSERTLISP + (verilog-auto-re-search-do "/\\*AUTOUNDEF\\((\"[^\"]*\")\\)?\\*/" 'verilog-auto-undef) ;; Wires/regs must be after inputs/outputs (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic) (verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire) @@ -12326,7 +12631,9 @@ Wilson Snyder (wsnyder@wsnyder.org)." (verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg) ;; Fix line numbers (comments only) (when verilog-auto-inst-template-numbers - (verilog-auto-templated-rel)))) + (verilog-auto-templated-rel)) + (when verilog-auto-template-warn-unused + (verilog-auto-template-lint)))) ;; (verilog-run-hooks 'verilog-auto-hook) ;; @@ -12343,9 +12650,8 @@ Wilson Snyder (wsnyder@wsnyder.org)." ;; End of after-change protection ))) ;; Unwind forms - (progn - ;; Restore font-lock - (when fontlocked (font-lock-mode t)))))) + ;; Currently handled in verilog-save-font-mods + )))) ;; @@ -12650,7 +12956,7 @@ and the case items." (define-skeleton verilog-sk-def-reg "Insert a reg definition." () - > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) ) + > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations-auto) ) (defun verilog-sk-define-signal () "Insert a definition of signal under point at top of module." @@ -12914,9 +13220,12 @@ Files are checked based on `verilog-library-flags'." (concat "verilog-mode v" verilog-mode-version) '( verilog-active-low-regexp + verilog-after-save-font-hook verilog-align-ifelse verilog-assignment-delay verilog-auto-arg-sort + verilog-auto-declare-nettype + verilog-auto-delete-trailing-whitespace verilog-auto-endcomments verilog-auto-hook verilog-auto-ignore-concat @@ -12925,23 +13234,32 @@ Files are checked based on `verilog-library-flags'." verilog-auto-input-ignore-regexp verilog-auto-inst-column verilog-auto-inst-dot-name + verilog-auto-inst-interfaced-ports verilog-auto-inst-param-value + verilog-auto-inst-sort verilog-auto-inst-template-numbers verilog-auto-inst-vector verilog-auto-lineup verilog-auto-newline verilog-auto-output-ignore-regexp verilog-auto-read-includes + verilog-auto-reset-blocking-in-non verilog-auto-reset-widths verilog-auto-save-policy verilog-auto-sense-defines-constant verilog-auto-sense-include-inputs verilog-auto-star-expand verilog-auto-star-save + verilog-auto-template-warn-unused + verilog-auto-tieoff-declaration + verilog-auto-tieoff-ignore-regexp verilog-auto-unused-ignore-regexp + verilog-auto-wire-type verilog-before-auto-hook verilog-before-delete-auto-hook verilog-before-getopt-flags-hook + verilog-before-save-font-hook + verilog-cache-enabled verilog-case-indent verilog-cexp-indent verilog-compiler @@ -12949,6 +13267,8 @@ Files are checked based on `verilog-library-flags'." verilog-delete-auto-hook verilog-getopt-flags-hook verilog-highlight-grouping-keywords + verilog-highlight-includes + verilog-highlight-modules verilog-highlight-p1800-keywords verilog-highlight-translate-off verilog-indent-begin-after-if @@ -12966,11 +13286,15 @@ Files are checked based on `verilog-library-flags'." verilog-linter verilog-minimum-comment-distance verilog-mode-hook + verilog-mode-release-date + verilog-mode-release-emacs + verilog-mode-version verilog-preprocessor verilog-simulator verilog-tab-always-indent verilog-tab-to-comment verilog-typedef-regexp + verilog-warn-fatal ) nil nil (concat "Hi Mac, -- 2.39.2