From: Wilson Snyder Date: Wed, 15 Sep 2021 01:21:03 +0000 (-0400) Subject: verilog-mode.el: Update verilog-mode from upstream. X-Git-Tag: emacs-28.0.90~967 X-Git-Url: http://git.eshelyaron.com/gitweb/?a=commitdiff_plain;h=e4fdf87e713d1161ebeca56c3c1d93bd971bd7f5;p=emacs.git verilog-mode.el: Update verilog-mode from upstream. * lisp/progmodes/verilog-mode.el: (verilog-basic-complete-re) (verilog-behavioral-block-beg-re, verilog-defun-keywords) (verilog-defun-level-generate-only-re, verilog-defun-level-re) (verilog-endcomment-reason-re, verilog-indent-re) (verilog-keywords, verilog-no-indent-begin-re) (verilog-set-auto-endcomments): Support Verilog-A `analog` blocks (#1738). Reported by Dan McMahill. (verilog-read-defines): Fix verilog-read-defines to work with SystemVerilog types (#1734). Reported by Shareef Jalloq. (verilog-indent-declaration, verilog-pretty-declarations): Fix leaving extra spaces before tabs on lining up declarations. (#1723) Reported by TAKAI Kousuke. (verilog-auto-inst, verilog-auto-inst-port) (verilog-read-auto-template-middle, verilog-read-sub-decls-line): Support AUTONOHOOKUP to not AUTOWIRE hookup AUTO_TEMPLATE signals. (#1526) Reported by firefoxtc. --- diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el index 7c8ccea065e..5cc834f4a89 100644 --- a/lisp/progmodes/verilog-mode.el +++ b/lisp/progmodes/verilog-mode.el @@ -9,7 +9,7 @@ ;; Keywords: languages ;; The "Version" is the date followed by the decimal rendition of the Git ;; commit hex. -;; Version: 2021.04.12.188864585 +;; Version: 2021.09.01.191709444 ;; Yoni Rabkin contacted the maintainer of this ;; file on 19/3/2008, and the maintainer agreed that when a bug is @@ -124,7 +124,7 @@ ;; ;; This variable will always hold the version number of the mode -(defconst verilog-mode-version "2021-04-12-b41d849-vpo-GNU" +(defconst verilog-mode-version "2021-09-01-b6d4104-vpo-GNU" "Version of this Verilog mode.") (defconst verilog-mode-release-emacs t "If non-nil, this version of Verilog mode was released with Emacs itself.") @@ -829,7 +829,7 @@ The name of the function or case will be set between the braces." (defcustom verilog-auto-ignore-concat nil "Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc. This will exclude signals referenced as pin connections in {...} -or (...) from AUTOWIRE, AUTOOUTPUT and friends." +or (...) from AUTOWIRE, AUTOOUTPUT and friends. See also AUTONOHOOKUP." :group 'verilog-mode-actions :type 'boolean) (put 'verilog-auto-ignore-concat 'safe-local-variable #'verilog-booleanp) @@ -2077,8 +2077,7 @@ find the errors." (if (boundp 'compilation-error-regexp-systems-alist) (if (and (not (equal compilation-error-regexp-systems-list 'all)) - ;; eval required due to bug1700, XEmacs otherwise errors on compile - (not (eval "(member compilation-error-regexp-systems-list 'verilog)"))) + (not (member 'verilog compilation-error-regexp-systems-list))) (push 'verilog compilation-error-regexp-systems-list))) (if (boundp 'compilation-error-regexp-alist-alist) (if (not (assoc 'verilog compilation-error-regexp-alist-alist)) @@ -2505,7 +2504,7 @@ find the errors." (defconst verilog-no-indent-begin-re (eval-when-compile (verilog-regexp-words - '("always" "always_comb" "always_ff" "always_latch" "initial" "final" ; procedural blocks + '("always" "always_comb" "always_ff" "always_latch" "analog" "initial" "final" ; procedural blocks "if" "else" ; conditional statements "while" "for" "foreach" "repeat" "do" "forever" )))) ; loop statements @@ -2651,6 +2650,7 @@ find the errors." "\\(\\\\s-+\\\\)\\|" ; 3 "\\(\\\\(?:[ \t]*@\\)\\)\\|" ; 4 (matches always or always_ff w/ @...) "\\(\\\\)\\|" ; 5 (matches always, always_comb, always_latch w/o @...) + "\\(\\\\)\\|" ; 6 "\\(\\\\)\\|" ; 7 "\\(\\\\)\\|" verilog-property-re "\\|" @@ -2853,7 +2853,7 @@ find the errors." (eval-when-compile (verilog-regexp-words '("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced")))) (defconst verilog-behavioral-block-beg-re - (eval-when-compile (verilog-regexp-words '("initial" "final" "always" "always_comb" "always_latch" "always_ff" + (eval-when-compile (verilog-regexp-words '("initial" "final" "always" "always_comb" "always_latch" "always_ff" "analog" "function" "task")))) (defconst verilog-coverpoint-re "\\w+\\s-*:\\s-*\\(coverpoint\\|cross\\|constraint\\)") (defconst verilog-in-constraint-re ; keywords legal in constraint blocks starting a statement/block @@ -2864,7 +2864,7 @@ find the errors." (verilog-regexp-words '( "{" - "always" "always_latch" "always_ff" "always_comb" + "always" "always_latch" "always_ff" "always_comb" "analog" "begin" "end" ;; "unique" "priority" "case" "casex" "casez" "randcase" "endcase" @@ -2956,13 +2956,13 @@ find the errors." '( "connectmodule" "module" "macromodule" "primitive" "class" "program" "interface" "package" "config") '( "initial" "final" "always" "always_comb" "always_ff" - "always_latch" "endtask" "endfunction" ))))) + "always_latch" "analog" "endtask" "endfunction" ))))) (defconst verilog-defun-level-generate-only-re (eval-when-compile (verilog-regexp-words '( "initial" "final" "always" "always_comb" "always_ff" - "always_latch" "endtask" "endfunction" )))) + "always_latch" "analog" "endtask" "endfunction" )))) (defconst verilog-cpp-level-re (eval-when-compile @@ -2989,7 +2989,7 @@ find the errors." (eval-when-compile (verilog-regexp-words '( - "always" "assign" "always_latch" "always_ff" "always_comb" "connectmodule" "constraint" + "always" "assign" "always_latch" "always_ff" "always_comb" "analog" "connectmodule" "constraint" "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while" "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert" )))) @@ -3066,7 +3066,7 @@ find the errors." (defconst verilog-keywords (append verilog-compiler-directives '( - "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and" + "after" "alias" "always" "always_comb" "always_ff" "always_latch" "analog" "and" "assert" "assign" "assume" "automatic" "before" "begin" "bind" "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte" "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos" @@ -3283,7 +3283,7 @@ See also `verilog-font-lock-extra-types'.") "use" "wait" "while" ;; 1800-2005 "alias" "always_comb" "always_ff" "always_latch" "assert" - "assume" "before" "bind" "bins" "binsof" "break" "class" + "assume" "analog" "before" "bind" "bins" "binsof" "break" "class" "clocking" "constraint" "context" "continue" "cover" "covergroup" "coverpoint" "cross" "dist" "do" "endclass" "endclocking" "endgroup" "endinterface" "endpackage" @@ -5104,7 +5104,7 @@ primitive or interface named NAME." (throw 'skip 1))))))))) (; always, always_comb, always_latch w/o @... - (match-end 5) + (or (match-end 5) (match-end 6)) (goto-char (match-end 0)) (setq there (point)) (setq err nil) @@ -7157,11 +7157,11 @@ Be verbose about progress unless optional QUIET set." (forward-char -1) (just-one-space) (goto-char (marker-position m1)) - (just-one-space) - (indent-to ind)) + (delete-horizontal-space) + (indent-to ind 1)) (progn - (just-one-space) - (indent-to ind))))) + (delete-horizontal-space) + (indent-to ind 1))))) ((verilog-continued-line-1 (marker-position startpos)) (goto-char e) (indent-line-to ind)) @@ -7324,12 +7324,10 @@ BASEIND is the base indent to offset everything." (forward-char -1) (just-one-space) (goto-char (marker-position m1)) - (just-one-space) - (indent-to ind)) - (if (/= (current-column) ind) - (progn - (just-one-space) - (indent-to ind))))) + (delete-horizontal-space) + (indent-to ind 1)) + (delete-horizontal-space) + (indent-to ind 1))) (if (looking-at verilog-declaration-re-2-no-macro) (let ((p (match-end 0))) (set-marker m1 p) @@ -7338,12 +7336,10 @@ BASEIND is the base indent to offset everything." (forward-char -1) (just-one-space) (goto-char (marker-position m1)) - (just-one-space) - (indent-to ind)) - (if (/= (current-column) ind) - (progn - (just-one-space) - (indent-to ind)))))))))) + (delete-horizontal-space) + (indent-to ind 1)) + (delete-horizontal-space) + (indent-to ind 1)))))))) (goto-char pos))) (defun verilog-get-lineup-indent (b edpos) @@ -7457,7 +7453,7 @@ will be completed at runtime and should not be added to this list.") (defvar verilog-defun-keywords (append '( - "always" "always_comb" "always_ff" "always_latch" "assign" + "always" "always_comb" "always_ff" "always_latch" "analog" "assign" "begin" "end" "connectmodule" "endconnectmodule" "generate" "endgenerate" "module" "endmodule" "specify" "endspecify" "function" "endfunction" "initial" "final" "task" "endtask" "primitive" "endprimitive" @@ -9106,9 +9102,7 @@ Inserts the list of signals found, using submodi to look up each port." ;; We intentionally ignore (non-escaped) signals with .s in them ;; this prevents AUTOWIRE etc from noticing hierarchical sigs. (when port - (cond ((and verilog-auto-ignore-concat - (looking-at "[({]")) - nil) ; {...} or (...) historically ignored with auto-ignore-concat + (cond ((looking-at "[^\n]*AUTONOHOOKUP")) ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)") (verilog-read-sub-decls-sig submoddecls par-values comment port @@ -9555,7 +9549,10 @@ Returns REGEXP and list of ( (signal_name connection_name)... )." (cons (list (match-string-no-properties 1) (match-string-no-properties 2) - templateno lineno) + templateno lineno + (save-excursion + (goto-char (match-end 0)) + (looking-at "[^\n]*AUTONOHOOKUP"))) tpl-sig-list)) (goto-char (match-end 0))) ;; Regexp form?? @@ -9571,7 +9568,10 @@ Returns REGEXP and list of ( (signal_name connection_name)... )." (match-string 1)) "$") rep - templateno lineno) + templateno lineno + (save-excursion + (goto-char (match-end 0)) + (looking-at "[^\n]*AUTONOHOOKUP"))) tpl-wild-list))) ((looking-at "[ \t\f]+") (goto-char (match-end 0))) @@ -9745,6 +9745,9 @@ warning message, you need to add to your init file: (while (re-search-forward "^\\s-*\\(parameter\\|localparam\\)\\(\\s-*\\[[^]]*\\]\\)?\\s-*" nil t) (let (enumname) + ;; Advance over parameter's type if present + (if (looking-at "\\([a-zA-Z0-9_]+\\s-+\\)[a-zA-Z0-9_]+") + (goto-char (match-end 1))) ;; The primary way of getting defines is verilog-read-decls ;; However, that isn't called yet for included files, so we'll add another scheme (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") @@ -11040,7 +11043,7 @@ Intended for internal use inside a 'verilog-delete-auto-star-all) ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed (goto-char (point-min)) - (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)\\([ \tLT0-9]*\\| LHS: .*\\)$" nil t) + (while (re-search-forward "\\s-*// \\(Templated\\(\\s-*AUTONOHOOKUP\\)?\\|Implicit \\.\\*\\)\\([ \tLT0-9]*\\| LHS: .*\\)$" nil t) (replace-match "")) ;; Final customize @@ -11689,15 +11692,14 @@ If PAR-VALUES replace final strings with these parameter values." ;; verilog-insert requires the complete comment in one call - including the newline (cond ((equal verilog-auto-inst-template-numbers 'lhs) (verilog-insert " // Templated" - " LHS: " (nth 0 tpl-ass) - "\n")) + " LHS: " (nth 0 tpl-ass))) (verilog-auto-inst-template-numbers (verilog-insert " // Templated" " T" (int-to-string (nth 2 tpl-ass)) - " L" (int-to-string (nth 3 tpl-ass)) - "\n")) + " L" (int-to-string (nth 3 tpl-ass)))) (t - (verilog-insert " // Templated\n")))) + (verilog-insert " // Templated"))) + (verilog-insert (if (nth 4 tpl-ass) " AUTONOHOOKUP\n" "\n"))) (for-star (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16) verilog-auto-inst-column)) @@ -12087,6 +12089,16 @@ Lisp Templates: After the evaluation is completed, @ substitution and [] substitution occur. + +Ignoring Hookup: + + AUTOWIRE and related AUTOs will read the signals created by a template. + To specify that a signal should not be parsed to participate in this + hookup, add a AUTONOHOOKUP comment to the template. For example: + + .pci_req_l (pci_req_not_to_wire), //AUTONOHOOKUP + + For more information see the \\[verilog-faq] and forums at URL `https://www.veripool.org'." (save-excursion