+2014-12-09 Wilson Snyder <wsnyder@wsnyder.org>
+
+ Sync with upstream verilog-mode revision aa4b777.
+ * progmodes/verilog-mode.el (verilog-mode-version): Update.
+ (verilog-auto-end-comment-lines-re, verilog-end-block-ordered-re)
+ (verilog-set-auto-endcomments): Automatically comment property/
+ endproperty blocks to match other similar blocks like sequence/
+ endsequence, function/endfunction, etc. Reported by Alex Reed.
+ (verilog-set-auto-endcomments): Fix end comments for functions of
+ type void, etc. Detect the function- or task-name when
+ auto-commenting blocks that lack an explicit portlist.
+ Reported by Alex Reed.
+ (verilog-nameable-item-re): Fix nameable items that can have an
+ end-identifier to include endchecker, endgroup, endprogram,
+ endproperty, and endsequence. Reported by Alex Reed.
+ (verilog-preprocessor-re, verilog-beg-of-statement):
+ Fix indentation of property/endproperty around pre-processor
+ directives. Reported by Alex Reed.
+ (verilog-label-be): When auto-commenting a buffer, consider
+ auto-comments on all known keywords (not just a subset thereof).
+ Reported by Alex Reed.
+ (verilog-beg-of-statement): Fix labeling do-while blocks, bug842.
+ Reported by Alex Reed.
+ (verilog-beg-of-statement-1, verilog-at-constraint-p):
+ Fix hanging with many curly-bracket pairs, bug663.
+ (verilog-do-indent): Fix electric tab deleting form-feeds.
+ Note caused by indent-line-to deleting tabls pre 24.5.
+ (verilog-auto-output, verilog-auto-input, verilog-auto-inout)
+ (verilog-auto-inout-module, verilog-auto-inout-in): Doc fixes.
+ (verilog-read-always-signals, verilog-auto-sense-sigs)
+ (verilog-auto-reset): Fix AUTORESET with always_comb and always_latch,
+ bug844. Reported by Greg Hilton.
+
+2014-12-09 Alex Reed <acreed4@gmail.com> (tiny change)
+
+ * progmodes/verilog-mode.el (verilog-no-indent-begin-re):
+ Fix `verilog-indent-begin-after-if' nil not honoring 'forever',
+ 'foreach', and 'do' keywords.
+ (verilog-endcomment-reason-re, verilog-beg-of-statement):
+ Fix labeling do-while blocks, bug842.
+ (verilog-backward-token): Fix indenting sensitivity lists with
+ named events, bug840.
+
2014-12-09 Reto Zimmermann <reto@gnu.org>
Sync with upstream vhdl mode v3.36.1.
;;; Code:
;; This variable will always hold the version number of the mode
-(defconst verilog-mode-version "2014-10-03-c075a49-vpo"
+(defconst verilog-mode-version "2014-11-12-aa4b777-vpo"
"Version of this Verilog mode.")
(defconst verilog-mode-release-emacs t
"If non-nil, this version of Verilog mode was released with Emacs itself.")
(defconst verilog-no-indent-begin-re
(eval-when-compile
(verilog-regexp-words
- '( "if" "else" "while" "for" "repeat" "always" "always_comb" "always_ff" "always_latch"
- "initial" "final"))))
+ '("always" "always_comb" "always_ff" "always_latch" "initial" "final" ;; procedural blocks
+ "if" "else" ;; conditional statements
+ "while" "for" "foreach" "repeat" "do" "forever" )))) ;; loop statements
(defconst verilog-ends-re
;; Parenthesis indicate type of keyword found
"endinterface"
"endpackage"
"endsequence"
+ "endproperty"
"endspecify"
"endtable"
"endtask"
"\\(program\\)\\|" ; 13
"\\(sequence\\)\\|" ; 14
"\\(clocking\\)\\|" ; 15
+ "\\(property\\)\\|" ; 16
"\\)\\>\\)"))
(defconst verilog-end-block-re
(eval-when-compile
"\\(\\<package\\>\\)\\|"
"\\(\\<final\\>\\)\\|"
"\\(@\\)\\|"
- "\\(\\<while\\>\\)\\|"
+ "\\(\\<while\\>\\)\\|\\(\\<do\\>\\)\\|"
"\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
"\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
"#"))
"join" "join_any" "join_none"
"end"
"endcase"
- "endconfig"
+ "endchecker"
"endclass"
"endclocking"
+ "endconfig"
"endfunction"
"endgenerate"
+ "endgroup"
"endmodule"
"endprimitive"
"endinterface"
"endpackage"
+ "endprogram"
+ "endproperty"
+ "endsequence"
"endspecify"
"endtable"
"endtask" )
"String used to mark end of excluded text.")
(defconst verilog-preprocessor-re
(eval-when-compile
- (verilog-regexp-words
- `(
- "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
- ))))
+ (concat
+ ;; single words
+ "\\(?:"
+ (verilog-regexp-words
+ `("`__FILE__"
+ "`__LINE__"
+ "`celldefine"
+ "`else"
+ "`end_keywords"
+ "`endcelldefine"
+ "`endif"
+ "`nounconnected_drive"
+ "`resetall"
+ "`unconnected_drive"
+ "`undefineall"))
+ "\\)\\|\\(?:"
+ ;; two words: i.e. `ifdef DEFINE
+ "\\<\\(`elsif\\|`ifn?def\\|`undef\\|`default_nettype\\|`begin_keywords\\)\\>\\s-"
+ "\\)\\|\\(?:"
+ ;; `line number "filename" level
+ "\\<\\(`line\\)\\>\\s-+[0-9]+\\s-+\"[^\"]+\"\\s-+[012]"
+ "\\)\\|\\(?:"
+ ;;`include "file" or `include <file>
+ "\\<\\(`include\\)\\>\\s-+\\(?:\"[^\"]+\"\\|<[^>]+>\\)"
+ "\\)\\|\\(?:"
+ ;; `pragma <stuff> (no mention in IEEE 1800-2012 that pragma can span multiple lines
+ "\\<\\(`pragma\\)\\>\\s-+.+$"
+ "\\)\\|\\(?:"
+ ;; `timescale time_unit / time_precision
+ "\\<\\(`timescale\\)\\>\\s-+10\\{0,2\\}\\s-*[munpf]?s\\s-*\\/\\s-*10\\{0,2\\}\\s-*[munpf]?s"
+ "\\)\\|\\(?:"
+ ;; `define and `if can span multiple lines if line ends in '\'. NOTE: `if is not IEEE 1800-2012
+ ;; from http://www.emacswiki.org/emacs/MultilineRegexp
+ (concat "\\<\\(`define\\|`if\\)\\>" ;; directive
+ "\\s-+" ;; separator
+ "\\(.*\\(?:\n.*\\)*?\\)" ;; definition: to tend of line, the maybe more lines (excludes any trailing \n)
+ "\\(?:\n\\s-*\n\\|\\'\\)") ;; blank line or EOF
+ "\\)"
+ )))
(defconst verilog-keywords
'( "`case" "`default" "`define" "`else" "`endfor" "`endif"
(while (and
(> (marker-position e) (point))
(verilog-re-search-forward
- (concat
- "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
- "\\|\\(`endif\\)\\|\\(`else\\)")
+ verilog-auto-end-comment-lines-re
nil 'move))
(goto-char (match-beginning 0))
(let ((indent-str (verilog-indent-line)))
;; or the token before us unambiguously ends a statement,
;; then move back a token and test again.
(not (or
- ;; stop if beginning of buffer
- (bolp)
- ;; stop if we find a ;
+ ;; stop if beginning of buffer
+ (bobp)
+ ;; stop if we find a ;
(= (preceding-char) ?\;)
- ;; stop if we see a named coverpoint
+ ;; stop if we see a named coverpoint
(looking-at "\\w+\\W*:\\W*\\(coverpoint\\|cross\\|constraint\\)")
- ;; keep going if we are in the middle of a word
+ ;; keep going if we are in the middle of a word
(not (or (looking-at "\\<") (forward-word -1)))
- ;; stop if we see an assertion (perhaps labeled)
+ ;; stop if we see an assertion (perhaps labeled)
(and
(looking-at "\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
(progn
- (setq h (point))
- (save-excursion
- (verilog-backward-token)
- (if (looking-at verilog-label-re)
- (setq h (point))))
- (goto-char h)))
- ;; stop if we see an extended complete reg, perhaps a complete one
+ (setq h (point))
+ (save-excursion
+ (verilog-backward-token)
+ (if (looking-at verilog-label-re)
+ (setq h (point))))
+ (goto-char h)))
+ ;; stop if we see an extended complete reg, perhaps a complete one
(and
- (looking-at verilog-complete-reg)
- (let* ((p (point)))
- (while (and (looking-at verilog-extended-complete-re)
- (progn (setq p (point))
- (verilog-backward-token)
- (/= p (point)))))
- (goto-char p)))
- ;; stop if we see a complete reg (previous found extended ones)
+ (looking-at verilog-complete-reg)
+ (let* ((p (point)))
+ (while (and (looking-at verilog-extended-complete-re)
+ (progn (setq p (point))
+ (verilog-backward-token)
+ (/= p (point)))))
+ (goto-char p)))
+ ;; stop if we see a complete reg (previous found extended ones)
(looking-at verilog-basic-complete-re)
- ;; stop if previous token is an ender
+ ;; stop if previous token is an ender
(save-excursion
- (verilog-backward-token)
- (or
- (looking-at verilog-end-block-re)
- (looking-at verilog-preprocessor-re))))) ;; end of test
- (verilog-backward-syntactic-ws)
- (verilog-backward-token))
+ (verilog-backward-token)
+ (looking-at verilog-end-block-re))))
+ (verilog-backward-syntactic-ws)
+ (verilog-backward-token))
;; Now point is where the previous line ended.
- (verilog-forward-syntactic-ws)))
+ (verilog-forward-syntactic-ws)
+ ;; Skip forward over any preprocessor directives, as they have wacky indentation
+ (if (looking-at verilog-preprocessor-re)
+ (progn (goto-char (match-end 0))
+ (verilog-forward-syntactic-ws)))))
(defun verilog-beg-of-statement-1 ()
"Move backward to beginning of statement."
(verilog-backward-syntactic-ws)
(if (or (bolp)
(= (preceding-char) ?\;)
- (save-excursion
+ (progn
(verilog-backward-token)
(looking-at verilog-ends-re)))
(progn
(goto-char pt)
- (throw 'done t))
- (verilog-backward-token))))
+ (throw 'done t)))))
(verilog-forward-syntactic-ws)))
;
; (while (and
(cond
((match-end 5) ;; of verilog-end-block-ordered-re
(setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
- (setq name-re "\\w+\\s-*("))
+ (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
((match-end 6) ;; of verilog-end-block-ordered-re
(setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
- (setq name-re "\\w+\\s-*("))
+ (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
((match-end 7) ;; of verilog-end-block-ordered-re
(setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
((match-end 8) ;; of verilog-end-block-ordered-re
(setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
((match-end 15) ;; of verilog-end-block-ordered-re
(setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
+ ((match-end 16) ;; of verilog-end-block-ordered-re
+ (setq reg "\\(\\<property\\>\\)\\|\\<endproperty\\>"))
(t (error "Problem in verilog-set-auto-endcomments")))
(let (b e)
(;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
t
(forward-word -1)
- (while (= (preceding-char) ?\_)
+ (while (or (= (preceding-char) ?\_)
+ (= (preceding-char) ?\@)
+ (= (preceding-char) ?\.))
(forward-word -1))
(cond
((looking-at "\\<else\\>")
(defun verilog-at-constraint-p ()
"If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
(if (save-excursion
+ (let ((p (point)))
(and
(equal (char-after) ?\{)
(forward-list)
(progn (backward-char 1)
(verilog-backward-ws&directives)
+ (and
(or (equal (char-before) ?\{) ;; empty case
(equal (char-before) ?\;)
- (equal (char-before) ?\})))))
+ (equal (char-before) ?\}))
+ ;; skip what looks like bus repitition operator {#{
+ (not (string-match "^{\\s-*[0-9]+\\s-*{" (buffer-substring p (point)))))))))
(progn
(let ( (pt (point)) (pass 0))
(verilog-backward-ws&directives)
(looking-at verilog-declaration-re))
(verilog-indent-declaration ind))
+ (;-- form feeds - ignored as bug in indent-line-to in < 24.5
+ (looking-at "\f"))
+
(;-- Everything else
t
(let ((val (eval (cdr (assoc type verilog-indent-alist)))))
(save-excursion
(let* (;;(dbg "")
sigs-out-d sigs-out-i sigs-out-unk sigs-temp sigs-in)
- (search-forward ")")
(verilog-read-always-signals-recurse nil nil nil)
(setq sigs-out-i (append sigs-out-i sigs-out-unk)
sigs-out-unk nil)
Typedefs must match `verilog-typedef-regexp', which is disabled by default.
+ Types are added to declarations if an AUTOLOGIC or
+ `verilog-auto-wire-type' is set to logic.
+
Signals matching `verilog-auto-output-ignore-regexp' are not included.
An example (see `verilog-auto-inst' for what else is going on here):
Typedefs must match `verilog-typedef-regexp', which is disabled by default.
+ Types are added to declarations if an AUTOLOGIC or
+ `verilog-auto-wire-type' is set to logic.
+
Signals matching `verilog-auto-input-ignore-regexp' are not included.
An example (see `verilog-auto-inst' for what else is going on here):
Typedefs must match `verilog-typedef-regexp', which is disabled by default.
+ Types are added to declarations if an AUTOLOGIC or
+ `verilog-auto-wire-type' is set to logic.
+
Signals matching `verilog-auto-inout-ignore-regexp' are not included.
An example (see `verilog-auto-inst' for what else is going on here):
/*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
-You may also provide an optional second regular expression, in
-which case only signals which have that pin direction and data
-type will be included. This matches against everything before
-the signal name in the declaration, for example against
-\"input\" (single bit), \"output logic\" (direction and type) or
-\"output [1:0]\" (direction and implicit type). You also
-probably want to skip spaces in your regexp.
+You may also provide an optional third argument regular
+expression, in which case only signals which have that pin
+direction and data type matching that regular expression will be
+included. This matches against everything before the signal name
+in the declaration, for example against \"input\" (single bit),
+\"output logic\" (direction and type) or \"output
+[1:0]\" (direction and implicit type). You also probably want to
+skip spaces in your regexp.
For example, the below will result in matching the output \"o\"
against the previous example's module:
signals matching the regular expression will be included. For example the
same expansion will result from only extracting signals starting with i:
- /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
+ /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/
+
+You may also provide an optional third argument regular
+expression, in which case only signals which have that pin
+direction and data type matching that regular expression will be
+included. This matches against everything before the signal name
+in the declaration, for example against \"input\" (single bit),
+\"output logic\" (direction and type) or \"output
+[1:0]\" (direction and implicit type). You also probably want to
+skip spaces in your regexp.
+
+For example, the below will result in matching the output \"o\"
+against the previous example's module:
+
+ /*AUTOINOUTCOMP(\"ExampMain\",\"\",\"^output.*\")*/"
(verilog-auto-inout-module t nil))
(defun verilog-auto-inout-in ()
signals matching the regular expression will be included. For example the
same expansion will result from only extracting signals starting with i:
- /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
+ /*AUTOINOUTIN(\"ExampMain\",\"^i\")*/"
(verilog-auto-inout-module nil t))
(defun verilog-auto-inout-param ()
(defun verilog-auto-sense-sigs (moddecls presense-sigs)
"Return list of signals for current AUTOSENSE block."
- (let* ((sigss (verilog-read-always-signals))
+ (let* ((sigss (save-excursion
+ (search-forward ")")
+ (verilog-read-always-signals)))
(sig-list (verilog-signals-not-params
(verilog-signals-not-in (verilog-alw-get-inputs sigss)
(append (and (not verilog-auto-sense-include-inputs)
(save-excursion
(verilog-read-signals
(save-excursion
- (verilog-re-search-backward-quick "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
+ (verilog-re-search-backward-quick
+ "\\(@\\|\\<\\(begin\\|if\\|case\\|always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
(point))
(point)))))
(save-excursion
- (verilog-re-search-backward-quick "@" nil t)
+ (verilog-re-search-backward-quick "\\(@\\|\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
(setq sigss (verilog-read-always-signals)))
(setq dly-list (verilog-alw-get-outputs-delayed sigss))
(setq sig-list (verilog-signals-not-in (append
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