(verilog-read-decls): Fix AUTOINPUT/AUTOOUTPUT mis-including genvars.

diff --git a/lisp/ChangeLog b/lisp/ChangeLog
index 6aefa76f7d756596afc4f8373dfc12a4aef3b655..19488a7810b5de04eda95fa51f1ce6beb420c71f 100644 (file)
--- a/lisp/ChangeLog
+++ b/lisp/ChangeLog
@@ -1,3 +1,8 @@
+2008-03-18  Wilson Snyder  <wsnyder@wsnyder.org>
+
+       * verilog-mode.el (verilog-read-decls): Fix AUTOINPUT/AUTOOUTPUT
+       mis-including genvars.
+
 2008-03-18  Stefan Monnier  <monnier@iro.umontreal.ca>
 
        * vc-bzr.el (vc-bzr-log-view-mode, vc-bzr-annotate-command)

diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el
index b24ccdc5bad66584f0df9652fde3d3b48bd02663..40da7e14f0bec39ff10bc73bd182175b24cd877c 100644 (file)
--- a/lisp/progmodes/verilog-mode.el
+++ b/lisp/progmodes/verilog-mode.el
@@ -6071,7 +6071,8 @@ Return a array of [outputs inouts inputs wire reg assign const]."
                ((or (equal keywd "supply0")
                     (equal keywd "supply1")
                     (equal keywd "supply")
-                    (equal keywd "localparam"))
+                    (equal keywd "localparam")
+                    (equal keywd "genvar"))
                 (unless io (setq vec nil  enum nil  rvalue nil  signed nil  typedefed nil  multidim nil  sig-paren paren
                                  expect-signal 'sigs-const)))
                ((or (equal keywd "parameter"))