output OUT_t o;
endmodule
- module ExampInst;
+ module ExampParamVal1;
/*AUTOOUTPUT*/
// Beginning of automatic outputs
output OUT_t o;
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
- .i (i[WIDTH-1:0]),
- .o (o));
+ .o (o),
+ .i (i[WIDTH-1:0]));
+ endmodule
+
+ // Local Variables:
+ // verilog-typedef-regexp: \"_t$\"
+ // End:
Note even though WIDTH=10, the AUTOINST has left the parameter as
a symbolic name. Likewise the OUT_t is preserved as the name
If `verilog-auto-inst-param-value' is set, this will
instead expand to:
- module ExampInst;
+ module ExampParamVal1;
/*AUTOOUTPUT*/
// Beginning of automatic outputs
output upper_t o;
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
- .i (i[9:0]),
- .o (o));
+ .o (o),
+ .i (i[9:0]));
Note that the instantiation now has \"i[9:0]\" as the WIDTH
was expanded. Likewise the data type of \"o\" in the AUTOOUTPUT
One work around for this problem is to manually create // Inputs and //
Outputs comments above subcell signals, for example:
- module ModuleName (
- // Outputs
- .out (out),
- // Inputs
- .in (in));"
+ submod SubModuleName (
+ // Outputs
+ .out (out),
+ // Inputs
+ .in (in));"
(save-excursion
(let ((end-mod-point (verilog-get-end-of-defun))
st-point end-inst-point par-values
For example:
- module ExampInject (i, o);
- input i;
- input j;
- output o;
- always @ (i or j)
- o = i | j;
- InstModule instName
+ module ExampInject (i, o);
+ input i;
+ input j;
+ output o;
+ always @ (i or j)
+ o = i | j;
+ InstModule instName
(.foobar(baz),
- j(j));
- endmodule
-
-Typing \\[verilog-inject-auto] will make this into:
-
- module ExampInject (i, o/*AUTOARG*/
- // Inputs
- j);
- input i;
- output o;
- always @ (/*AS*/i or j)
- o = i | j;
- InstModule instName
+ .j(j));
+ endmodule
+
+Typing \\[verilog-inject-auto] (with an appropriate submodule not
+shown) will make this into:
+
+ module ExampInject (i, o/*AUTOARG*/
+ // Inputs
+ j);
+ input i;
+ output o;
+ always @ (/*AS*/i or j)
+ o = i | j;
+ InstModule instName
(.foobar(baz),
- /*AUTOINST*/
- // Outputs
- j(j));
- endmodule"
+ /*AUTOINST*/
+ // Outputs
+ j(j));
+ endmodule"
(interactive)
(verilog-auto t))
For example:
- module ExampArg (/*AUTOARG*/);
- input i;
- output o;
- endmodule
+ module ExampArg (/*AUTOARG*/);
+ input i;
+ output o;
+ endmodule
Typing \\[verilog-auto] will make this into:
- module ExampArg (/*AUTOARG*/
- // Outputs
- o,
- // Inputs
- i
- );
- input i;
- output o;
- endmodule
+ module ExampArg (/*AUTOARG*/
+ // Outputs
+ o,
+ // Inputs
+ i);
+ input i;
+ output o;
+ endmodule
The argument declarations may be printed in declaration order to
best suit order based instantiations, or alphabetically, based on
For example, first take the submodule InstModule.v:
- module InstModule (o,i);
- output [31:0] o;
- input i;
- wire [31:0] o = {32{i}};
- endmodule
+ module InstModule (o,i);
+ output [31:0] o;
+ input i;
+ wire [31:0] o = {32{i}};
+ endmodule
This is then used in an upper level module:
- module ExampInst (o,i);
- output o;
- input i;
- InstModule instName
- (/*AUTOINST*/);
- endmodule
+ module ExampInst (o,i);
+ output o;
+ input i;
+ InstModule instName
+ (/*AUTOINST*/);
+ endmodule
Typing \\[verilog-auto] will make this into:
- module ExampInst (o,i);
- output o;
- input i;
- InstModule instName
- (/*AUTOINST*/
- // Outputs
- .ov (ov[31:0]),
- // Inputs
- .i (i));
- endmodule
+ module ExampInst (o,i);
+ output o;
+ input i;
+ InstModule instName
+ (/*AUTOINST*/
+ // Outputs
+ .o (o[31:0]),
+ // Inputs
+ .i (i));
+ endmodule
Where the list of inputs and outputs came from the inst module.
\f
you have the appropriate // Input or // Output comment, and exactly the
same line formatting as AUTOINST itself uses.
- InstModule instName
+ InstModule instName
(// Inputs
- .i (my_i_dont_mess_with_it),
- /*AUTOINST*/
- // Outputs
- .ov (ov[31:0]));
+ .i (my_i_dont_mess_with_it),
+ /*AUTOINST*/
+ // Outputs
+ .o (o[31:0]));
\f
Templates:
For multiple instantiations based upon a single template, create a
commented out template:
- /* InstModule AUTO_TEMPLATE (
- .sig3 (sigz[]),
- );
- */
+ /* InstModule AUTO_TEMPLATE (
+ .sig3 (sigz[]),
+ );
+ */
Templates go ABOVE the instantiation(s). When an instantiation is
expanded `verilog-mode' simply searches up for the closest template.
For example:
- /* InstModule AUTO_TEMPLATE (
- .ptl_bus (ptl_busnew[]),
- );
- */
- InstModule ms2m (/*AUTOINST*/);
+ /* InstModule AUTO_TEMPLATE (
+ .ptl_bus (ptl_busnew[]),
+ );
+ */
+ InstModule ms2m (/*AUTOINST*/);
Typing \\[verilog-auto] will make this into:
- InstModule ms2m (/*AUTOINST*/
- // Outputs
- .NotInTemplate (NotInTemplate),
- .ptl_bus (ptl_busnew[3:0]), // Templated
- ....
+ InstModule ms2m (/*AUTOINST*/
+ // Outputs
+ .NotInTemplate (NotInTemplate),
+ .ptl_bus (ptl_busnew[3:0]), // Templated
+ ....
\f
Multiple Module Templates:
The same template lines can be applied to multiple modules with
the syntax as follows:
- /* InstModuleA AUTO_TEMPLATE
- InstModuleB AUTO_TEMPLATE
- InstModuleC AUTO_TEMPLATE
- InstModuleD AUTO_TEMPLATE (
- .ptl_bus (ptl_busnew[]),
- );
- */
+ /* InstModuleA AUTO_TEMPLATE
+ InstModuleB AUTO_TEMPLATE
+ InstModuleC AUTO_TEMPLATE
+ InstModuleD AUTO_TEMPLATE (
+ .ptl_bus (ptl_busnew[]),
+ );
+ */
Note there is only one AUTO_TEMPLATE opening parenthesis.
\f
It is common to instantiate a cell multiple times, so templates make it
trivial to substitute part of the cell name into the connection name.
- /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
- .sig1 (sigx[@]),
- .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
- );
- */
+ /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
+ .sig1 (sigx[@]),
+ .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
+ );
+ */
If no regular expression is provided immediately after the AUTO_TEMPLATE
keyword, then the @ character in any connection names will be replaced
For example:
- /* InstModule AUTO_TEMPLATE (
- .ptl_mapvalidx (ptl_mapvalid[@]),
- .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
- );
- */
- InstModule ms2m (/*AUTOINST*/);
+ /* InstModule AUTO_TEMPLATE (
+ .ptl_mapvalidx (ptl_mapvalid[@]),
+ .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
+ );
+ */
+ InstModule ms2m (/*AUTOINST*/);
Typing \\[verilog-auto] will make this into:
- InstModule ms2m (/*AUTOINST*/
- // Outputs
- .ptl_mapvalidx (ptl_mapvalid[2]),
- .ptl_mapvalidp1x (ptl_mapvalid[3]));
+ InstModule ms2m (/*AUTOINST*/
+ // Outputs
+ .ptl_mapvalidx (ptl_mapvalid[2]),
+ .ptl_mapvalidp1x (ptl_mapvalid[3]));
Note the @ character was replaced with the 2 from \"ms2m\".
Alternatively, using a regular expression for @:
- /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
- .ptl_mapvalidx (@_ptl_mapvalid),
- .ptl_mapvalidp1x (ptl_mapvalid_@),
- );
- */
- InstModule ms2_FOO (/*AUTOINST*/);
- InstModule ms2_BAR (/*AUTOINST*/);
+ /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
+ .ptl_mapvalidx (@_ptl_mapvalid),
+ .ptl_mapvalidp1x (ptl_mapvalid_@),
+ );
+ */
+ InstModule ms2_FOO (/*AUTOINST*/);
+ InstModule ms2_BAR (/*AUTOINST*/);
Typing \\[verilog-auto] will make this into:
- InstModule ms2_FOO (/*AUTOINST*/
- // Outputs
- .ptl_mapvalidx (FOO_ptl_mapvalid),
- .ptl_mapvalidp1x (ptl_mapvalid_FOO));
- InstModule ms2_BAR (/*AUTOINST*/
- // Outputs
- .ptl_mapvalidx (BAR_ptl_mapvalid),
- .ptl_mapvalidp1x (ptl_mapvalid_BAR));
+ InstModule ms2_FOO (/*AUTOINST*/
+ // Outputs
+ .ptl_mapvalidx (FOO_ptl_mapvalid),
+ .ptl_mapvalidp1x (ptl_mapvalid_FOO));
+ InstModule ms2_BAR (/*AUTOINST*/
+ // Outputs
+ .ptl_mapvalidx (BAR_ptl_mapvalid),
+ .ptl_mapvalidp1x (ptl_mapvalid_BAR));
\f
Regexp Templates:
A template entry of the form
- .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
+ .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
will apply an Emacs style regular expression search for any port beginning
in pci_req followed by numbers and ending in _l and connecting that to
completely different -- still use \\1 there!) Thus this is the same as
the above template:
- .pci_req@_l (pci_req_jtag_[\\1]),
+ .pci_req@_l (pci_req_jtag_[\\1]),
Here's another example to remove the _l, useful when naming conventions
specify _ alone to mean active low. Note the use of [] to keep the bus
subscript:
- .\\(.*\\)_l (\\1_[]),
+ .\\(.*\\)_l (\\1_[]),
\f
Lisp Templates:
There are special variables defined that are useful in these
Lisp functions:
- vl-name Name portion of the input/output port.
- vl-bits Bus bits portion of the input/output port (`[2:0]').
- vl-mbits Multidimensional array bits for port (`[2:0][3:0]').
- vl-width Width of the input/output port (`3' for [2:0]).
+ vl-name Name portion of the input/output port.
+ vl-bits Bus bits portion of the input/output port (`[2:0]').
+ vl-mbits Multidimensional array bits for port (`[2:0][3:0]').
+ vl-width Width of the input/output port (`3' for [2:0]).
May be a (...) expression if bits isn't a constant.
- vl-dir Direction of the pin input/output/inout/interface.
- vl-modport The modport, if an interface with a modport.
- vl-cell-type Module name/type of the cell (`InstModule').
- vl-cell-name Instance name of the cell (`instName').
+ vl-dir Direction of the pin input/output/inout/interface.
+ vl-modport The modport, if an interface with a modport.
+ vl-cell-type Module name/type of the cell (`InstModule').
+ vl-cell-name Instance name of the cell (`instName').
Normal Lisp variables may be used in expressions. See
`verilog-read-defines' which can set vh-{definename} variables for use
here. Also, any comments of the form:
- /*AUTO_LISP(setq foo 1)*/
+ /*AUTO_LISP(setq foo 1)*/
will evaluate any Lisp expression inside the parenthesis between the
beginning of the buffer and the point of the AUTOINST. This allows
For example, first take the submodule InstModule.v:
- module InstModule (o,i);
- parameter PAR;
- endmodule
+ module InstModule (o,i);
+ parameter PAR;
+ endmodule
This is then used in an upper level module:
- module ExampInst (o,i);
- parameter PAR;
- InstModule #(/*AUTOINSTPARAM*/)
- instName (/*AUTOINST*/);
- endmodule
+ module ExampInstParam (o,i);
+ parameter PAR;
+ InstModule #(/*AUTOINSTPARAM*/)
+ instName (/*AUTOINST*/);
+ endmodule
Typing \\[verilog-auto] will make this into:
- module ExampInst (o,i);
- output o;
- input i;
- InstModule #(/*AUTOINSTPARAM*/
- // Parameters
- .PAR (PAR));
- instName (/*AUTOINST*/);
- endmodule
+ module ExampInstParam (o,i);
+ parameter PAR;
+ InstModule #(/*AUTOINSTPARAM*/
+ // Parameters
+ .PAR (PAR))
+ instName (/*AUTOINST*/);
+ endmodule
Where the list of parameter connections come from the inst module.
\f
An example:
- module ExampReg (o,i);
- output o;
- input i;
- /*AUTOREG*/
- always o = i;
- endmodule
+ module ExampReg (o,i);
+ output o;
+ input i;
+ /*AUTOREG*/
+ always o = i;
+ endmodule
Typing \\[verilog-auto] will make this into:
- module ExampReg (o,i);
- output o;
- input i;
- /*AUTOREG*/
- // Beginning of automatic regs (for this module's undeclared outputs)
- reg o;
- // End of automatics
- always o = i;
- endmodule"
+ module ExampReg (o,i);
+ output o;
+ input i;
+ /*AUTOREG*/
+ // Beginning of automatic regs
+ reg o;
+ // End of automatics
+ always o = i;
+ endmodule"
(save-excursion
;; Point must be at insertion point.
(let* ((indent-pt (current-indentation))
An example (see `verilog-auto-inst' for what else is going on here):
- module ExampRegInput (o,i);
- output o;
- input i;
- /*AUTOREGINPUT*/
+ module InstModule (input i);
+ endmodule
+
+ module ExampRegInput ();
+ /*AUTOREGINPUT*/
InstModule instName
(/*AUTOINST*/);
- endmodule
+ endmodule
Typing \\[verilog-auto] will make this into:
- module ExampRegInput (o,i);
- output o;
- input i;
- /*AUTOREGINPUT*/
- // Beginning of automatic reg inputs (for undeclared ...
- reg [31:0] iv; // From inst of inst.v
- // End of automatics
- InstModule instName
+ module ExampRegInput ();
+ /*AUTOREGINPUT*/
+ // Beginning of automatic reg inputs
+ reg i; // To instName of InstModule.v
+ // End of automatics
+ InstModule instName
(/*AUTOINST*/
- // Outputs
- .o (o[31:0]),
- // Inputs
- .iv (iv));
- endmodule"
+ // Inputs
+ .i (i));
+ endmodule"
(save-excursion
;; Point must be at insertion point.
(let* ((indent-pt (current-indentation))
An example (see `verilog-auto-inst' for what else is going on here):
- module ExampWire (o,i);
- output o;
- input i;
- /*AUTOWIRE*/
+ module ExampWire (i);
+ input i;
+ /*AUTOWIRE*/
InstModule instName
- (/*AUTOINST*/);
- endmodule
+ (/*AUTOINST*/);
+ endmodule
Typing \\[verilog-auto] will make this into:
- module ExampWire (o,i);
- output o;
- input i;
- /*AUTOWIRE*/
- // Beginning of automatic wires
- wire [31:0] ov; // From inst of inst.v
- // End of automatics
- InstModule instName
- (/*AUTOINST*/
- // Outputs
- .ov (ov[31:0]),
- // Inputs
- .i (i));
- wire o = | ov;
- endmodule"
+ module ExampWire (i);
+ input i;
+ /*AUTOWIRE*/
+ // Beginning of automatic wires
+ wire [31:0] o; // From instName of InstModule.v
+ // End of automatics
+ InstModule instName
+ (/*AUTOINST*/
+ // Outputs
+ .o (o[31:0]),
+ // Inputs
+ .i (i));
+ wire o = | ov;
+ endmodule"
(save-excursion
;; Point must be at insertion point.
(let* ((indent-pt (current-indentation))
An example (see `verilog-auto-inst' for what else is going on here):
- module ExampOutput (ov,i);
- input i;
- /*AUTOOUTPUT*/
- InstModule instName
- (/*AUTOINST*/);
- endmodule
+ module InstModule (output o);
+ endmodule
+
+ module ExampOutput
+ (/*AUTOOUTPUT*/
+ );
+ InstModule instName
+ (/*AUTOINST*/);
+ endmodule
Typing \\[verilog-auto] will make this into:
- module ExampOutput (ov,i);
- input i;
- /*AUTOOUTPUT*/
- // Beginning of automatic outputs (from unused autoinst outputs)
- output [31:0] ov; // From inst of inst.v
- // End of automatics
- InstModule instName
- (/*AUTOINST*/
- // Outputs
- .ov (ov[31:0]),
- // Inputs
- .i (i));
- endmodule
+ module ExampOutput
+ (/*AUTOOUTPUT*/
+ // Beginning of automatic outputs
+ output o // From instName of InstModule.v
+ // End of automatics
+ );
+ InstModule instName
+ (/*AUTOINST*/
+ // Outputs
+ .o (o));
+ endmodule
You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
An example:
- module ExampOutputEvery (o,i,tempa,tempb);
- output o;
- input i;
- /*AUTOOUTPUTEVERY*/
- wire tempa = i;
- wire tempb = tempa;
- wire o = tempb;
- endmodule
+ module ExampOutputEvery (o,i,tempa,tempb);
+ output o;
+ input i;
+ /*AUTOOUTPUTEVERY*/
+ wire tempa = i;
+ wire tempb = tempa;
+ wire o = tempb;
+ endmodule
Typing \\[verilog-auto] will make this into:
- module ExampOutputEvery (o,i,tempa,tempb);
- output o;
- input i;
- /*AUTOOUTPUTEVERY*/
- // Beginning of automatic outputs (every signal)
- output tempb;
- output tempa;
- // End of automatics
- wire tempa = i;
- wire tempb = tempa;
- wire o = tempb;
- endmodule
+ module ExampOutputEvery (
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output o,
+ output tempa,
+ output tempb,
+ // End of automatics
+ input i
+ );
+ wire tempa = i;
+ wire tempb = tempa;
+ wire o = tempb;
+ endmodule
You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting outputs starting with ov:
- /*AUTOOUTPUTEVERY(\"^ov\")*/"
+ /*AUTOOUTPUTEVERY(\"^ov\")*/"
(save-excursion
;;Point must be at insertion point
(let* ((indent-pt (current-indentation))
An example (see `verilog-auto-inst' for what else is going on here):
- module ExampInput (ov,i);
- output [31:0] ov;
- /*AUTOINPUT*/
- InstModule instName
- (/*AUTOINST*/);
- endmodule
+ module InstModule (input i);
+ endmodule
+
+ module ExampInput (
+ /*AUTOINPUT*/
+ );
+ InstModule instName
+ (/*AUTOINST*/);
+ endmodule
Typing \\[verilog-auto] will make this into:
- module ExampInput (ov,i);
- output [31:0] ov;
- /*AUTOINPUT*/
- // Beginning of automatic inputs (from unused autoinst inputs)
- input i; // From inst of inst.v
- // End of automatics
- InstModule instName
- (/*AUTOINST*/
- // Outputs
- .ov (ov[31:0]),
- // Inputs
- .i (i));
- endmodule
+ module ExampInput (
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input i // To instName of InstModule.v
+ // End of automatics
+ );
+ InstModule instName
+ (/*AUTOINST*/
+ // Inputs
+ .i (i));
+ endmodule
You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
An example (see `verilog-auto-inst' for what else is going on here):
- module ExampInout (ov,i);
- input i;
- /*AUTOINOUT*/
- InstModule instName
- (/*AUTOINST*/);
- endmodule
+ module InstModule (inout io);
+ endmodule
+
+ module ExampInout (
+ /*AUTOINOUT*/
+ );
+ InstModule instName
+ (/*AUTOINST*/);
+ endmodule
Typing \\[verilog-auto] will make this into:
- module ExampInout (ov,i);
- input i;
- /*AUTOINOUT*/
- // Beginning of automatic inouts (from unused autoinst inouts)
- inout [31:0] ov; // From inst of inst.v
- // End of automatics
- InstModule instName
- (/*AUTOINST*/
- // Inouts
- .ov (ov[31:0]),
- // Inputs
- .i (i));
- endmodule
+ module ExampInout (
+ /*AUTOINOUT*/
+ // Beginning of automatic inouts
+ inout io // To/From instName of InstModule.v
+ // End of automatics
+ );
+ InstModule instName
+ (/*AUTOINST*/
+ // Inouts
+ .io (io));
+ endmodule
You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting inouts starting with i:
- /*AUTOINOUT(\"^i\")*/"
+ /*AUTOINOUT(\"^i\")*/"
(save-excursion
;; Point must be at insertion point.
(let* ((indent-pt (current-indentation))
An example:
- module ExampShell (/*AUTOARG*/);
- /*AUTOINOUTMODULE(\"ExampMain\")*/
- endmodule
+ module ExampMain
+ (input i,
+ output o,
+ inout io);
+ endmodule
- module ExampMain (i,o,io);
- input i;
- output o;
- inout io;
+ module ExampShell (/*AUTOARG*/);
+ /*AUTOINOUTMODULE(\"ExampMain\")*/
endmodule
Typing \\[verilog-auto] will make this into:
- module ExampShell (/*AUTOARG*/i,o,io);
- /*AUTOINOUTMODULE(\"ExampMain\")*/
- // Beginning of automatic in/out/inouts (from specific module)
+ module ExampShell (/*AUTOARG*/o, io, o);
+ /*AUTOINOUTMODULE(\"ExampMain\")*/
+ // Beginning of automatic in/out/inouts
output o;
inout io;
input i;
- // End of automatics
- endmodule
+ // End of automatics
+ endmodule
You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting signals starting with i:
- /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
+ /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
You may also provide an optional third argument regular
expression, in which case only signals which have that pin
For example, the below will result in matching the output \"o\"
against the previous example's module:
- /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/
+ /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/
You may also provide an optional fourth argument regular
expression, which if not \"\" only signals which do NOT match
An example:
- module ExampShell (/*AUTOARG*/);
- /*AUTOINOUTCOMP(\"ExampMain\")*/
- endmodule
+ module ExampMain
+ (input i,
+ output o,
+ inout io);
+ endmodule
- module ExampMain (i,o,io);
- input i;
- output o;
- inout io;
+ module ExampBench (/*AUTOARG*/);
+ /*AUTOINOUTCOMP(\"ExampMain\")*/
endmodule
Typing \\[verilog-auto] will make this into:
- module ExampShell (/*AUTOARG*/i,o,io);
- /*AUTOINOUTCOMP(\"ExampMain\")*/
- // Beginning of automatic in/out/inouts (from specific module)
+ module ExampShell (/*AUTOARG*/i, io, o);
+ /*AUTOINOUTCOMP(\"ExampMain\")*/
+ // Beginning of automatic in/out/inouts
output i;
inout io;
input o;
- // End of automatics
- endmodule
+ // End of automatics
+ endmodule
You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting signals starting with i:
- /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/
+ /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/
You may also provide an optional third argument regular
expression, in which case only signals which have that pin
For example, the below will result in matching the output \"o\"
against the previous example's module:
- /*AUTOINOUTCOMP(\"ExampMain\",\"\",\"^output.*\")*/
+ /*AUTOINOUTCOMP(\"ExampMain\",\"\",\"^output.*\")*/
You may also provide an optional fourth argument regular
expression, which if not \"\" only signals which do NOT match
An example:
- module ExampShell (/*AUTOARG*/);
- /*AUTOINOUTIN(\"ExampMain\")*/
- endmodule
+ module ExampMain
+ (input i,
+ output o,
+ inout io);
+ endmodule
- module ExampMain (i,o,io);
- input i;
- output o;
- inout io;
+ module ExampInoutIn (/*AUTOARG*/);
+ /*AUTOINOUTIN(\"ExampMain\")*/
endmodule
Typing \\[verilog-auto] will make this into:
- module ExampShell (/*AUTOARG*/i,o,io);
- /*AUTOINOUTIN(\"ExampMain\")*/
- // Beginning of automatic in/out/inouts (from specific module)
+ module ExampInoutIn (/*AUTOARG*/i, io, o);
+ /*AUTOINOUTIN(\"ExampMain\")*/
+ // Beginning of automatic in/out/inouts
input i;
input io;
input o;
- // End of automatics
- endmodule
+ // End of automatics
+ endmodule
You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting signals starting with i:
- /*AUTOINOUTIN(\"ExampMain\",\"^i\")*/"
+ /*AUTOINOUTIN(\"ExampMain\",\"^i\")*/"
(verilog-auto-inout-module nil t))
(defun verilog-auto-inout-param ()
An example:
- module ExampShell ();
- /*AUTOINOUTPARAM(\"ExampMain\")*/
- endmodule
-
- module ExampMain ();
+ module ExampMain ();
parameter PARAM = 22;
endmodule
+ module ExampInoutParam ();
+ /*AUTOINOUTPARAM(\"ExampMain\")*/
+ endmodule
+
Typing \\[verilog-auto] will make this into:
- module ExampShell (/*AUTOARG*/i,o,io);
- /*AUTOINOUTPARAM(\"ExampMain\")*/
+ module ExampInoutParam ();
+ /*AUTOINOUTPARAM(\"ExampMain\")*/
// Beginning of automatic parameters (from specific module)
- parameter PARAM;
- // End of automatics
- endmodule
+ parameter PARAM;
+ // End of automatics
+ endmodule
You may also provide an optional regular expression, in which case only
parameters matching the regular expression will be included. For example the
same expansion will result from only extracting parameters starting with i:
- /*AUTOINOUTPARAM(\"ExampMain\",\"^i\")*/"
+ /*AUTOINOUTPARAM(\"ExampMain\",\"^i\")*/"
(save-excursion
(let* ((params (verilog-read-auto-params 1 2))
(submod (nth 0 params))
An example:
- interface ExampIf
- ( input logic clk );
- logic req_val;
- logic [7:0] req_dat;
- clocking mon_clkblk @(posedge clk);
- input req_val;
- input req_dat;
- endclocking
- modport mp(clocking mon_clkblk);
- endinterface
-
- module ExampMain
- ( input clk,
- /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
- // Beginning of automatic in/out/inouts (from modport)
- input [7:0] req_dat,
- input req_val
- // End of automatics
- );
- /*AUTOASSIGNMODPORT(\"ExampIf\" \"mp\")*/
- endmodule
+ interface ExampIf
+ ( input logic clk );
+ logic req_val;
+ logic [7:0] req_dat;
+ clocking mon_clkblk @(posedge clk);
+ input req_val;
+ input req_dat;
+ endclocking
+ modport mp(clocking mon_clkblk);
+ endinterface
+
+ module ExampMain
+ ( input clk,
+ /*AUTOINOUTMODPORT(\"ExampIf\", \"mp\")*/
+ );
+ endmodule
Typing \\[verilog-auto] will make this into:
- ...
- module ExampMain
- ( input clk,
- /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
- // Beginning of automatic in/out/inouts (from modport)
- input req_dat,
- input req_val
- // End of automatics
- );
+ module ExampMain
+ ( input clk,
+ /*AUTOINOUTMODPORT(\"ExampIf\", \"mp\")*/
+ // Beginning of automatic in/out/inouts (from modport)
+ input req_val,
+ input [7:0] req_dat
+ // End of automatics
+ );
+ endmodule
If the modport is part of a UVM monitor/driver class, this
creates a wrapper module that may be used to instantiate the
An example:
- module ExampInsertLisp;
- /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
- endmodule
-
- // For this example we declare the function in the
- // module's file itself. Often you'd define it instead
- // in a site-start.el or init file.
- /*
- Local Variables:
- eval:
- (defun my-verilog-insert-hello (who)
- (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\")))
- End:
- */
+ module ExampInsertLisp;
+ /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
+ endmodule
+
+ // For this example we declare the function in the
+ // module's file itself. Often you'd define it instead
+ // in a site-start.el or init file.
+ /*
+ Local Variables:
+ eval:
+ (defun my-verilog-insert-hello (who)
+ (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\")))
+ End:
+ */
Typing \\[verilog-auto] will call my-verilog-insert-hello and
expand the above into:
- // Beginning of automatic insert lisp
- initial $write(\"hello world\");
- // End of automatics
+ /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
+ // Beginning of automatic insert lisp
+ initial $write(\"hello world\");
+ // End of automatics
You can also call an external program and insert the returned
text:
- /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/
- // Beginning of automatic insert lisp
- //hello
- // End of automatics"
+ /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/
+ // Beginning of automatic insert lisp
+ //hello
+ // End of automatics"
(save-excursion
;; Point is at end of /*AUTO...*/
(let* ((indent-pt (current-indentation))
An example:
- always @ (/*AS*/) begin
- /* AUTO_CONSTANT (\\=`constant) */
- outin = ina | inb | \\=`constant;
- out = outin;
- end
+ always @ (/*AS*/) begin
+ /*AUTO_CONSTANT (\\=`constant) */
+ outin = ina | inb | \\=`constant;
+ out = outin;
+ end
Typing \\[verilog-auto] will make this into:
- always @ (/*AS*/ina or inb) begin
- /* AUTO_CONSTANT (\\=`constant) */
- outin = ina | inb | \\=`constant;
- out = outin;
- end
+ always @ (/*AS*/ina or inb) begin
+ /*AUTO_CONSTANT (\\=`constant) */
+ outin = ina | inb | \\=`constant;
+ out = outin;
+ end
Note in Verilog 2001, you can often get the same result from the new @*
operator. (This was added to the language in part due to AUTOSENSE!)
- always @* begin
- outin = ina | inb | \\=`constant;
- out = outin;
- end"
+ always @* begin
+ outin = ina | inb | \\=`constant;
+ out = outin;
+ end"
(save-excursion
;; Find beginning
(let* ((start-pt (save-excursion
An example:
- always @(posedge clk or negedge reset_l) begin
- if (!reset_l) begin
- c <= 1;
- /*AUTORESET*/
- end
- else begin
- a <= in_a;
- b <= in_b;
- c <= in_c;
- end
- end
+ module ExampReset ();
+ always @(posedge clk or negedge reset_l) begin
+ if (!reset_l) begin
+ c <= 1;
+ /*AUTORESET*/
+ end
+ else begin
+ a <= in_a;
+ b <= in_b;
+ c <= in_c;
+ end
+ end
+ endmodule
Typing \\[verilog-auto] will make this into:
- always @(posedge core_clk or negedge reset_l) begin
- if (!reset_l) begin
- c <= 1;
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- a <= 0;
- b = 0; // if `verilog-auto-reset-blocking-in-non' true
- // End of automatics
- end
- else begin
- a <= in_a;
- b = in_b;
- c <= in_c;
- end
- end"
+ ...
+ c <= 1;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ a <= 1'h0;
+ b <= 1'h0;
+ // End of automatics
+ ..."
(interactive)
(save-excursion
An example of making a stub for another module:
- module ExampStub (/*AUTOINST*/);
- /*AUTOINOUTPARAM(\"Foo\")*/
- /*AUTOINOUTMODULE(\"Foo\")*/
- /*AUTOTIEOFF*/
- // verilator lint_off UNUSED
- wire _unused_ok = &{1\\='b0,
- /*AUTOUNUSED*/
- 1\\='b0};
- // verilator lint_on UNUSED
- endmodule
+ module ExampMain
+ #(parameter P)
+ (input i, output o, inout io);
+ endmodule
-Typing \\[verilog-auto] will make this into:
+ module ExampStub (/*AUTOARG*/);
+ /*AUTOINOUTPARAM(\"ExampMain\")*/
+ /*AUTOINOUTMODULE(\"ExampMain\")*/
- module ExampStub (/*AUTOINST*/...);
- /*AUTOINOUTPARAM(\"Foo\")*/
- /*AUTOINOUTMODULE(\"Foo\")*/
- // Beginning of autotieoff
- output [2:0] foo;
- // End of automatics
+ /*AUTOTIEOFF*/
+
+ // verilator lint_off UNUSED
+ wire _unused_ok = &{1\\='b0,
+ /*AUTOUNUSED*/
+ 1\\='b0};
+ // verilator lint_on UNUSED
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+ ...
/*AUTOTIEOFF*/
- // Beginning of autotieoff
- wire [2:0] foo = 3\\='b0;
+ // Beginning of automatic tieoffs
+ wire [2:0] o = 3\\='b0;
// End of automatics
- ...
- endmodule"
+ ..."
(interactive)
(save-excursion
;; Find beginning
An example:
- \\=`define XX_FOO
- \\=`define M_BAR(x)
- \\=`define M_BAZ
- ...
- \\=`ifdef NEVER
- \\=`undef M_BAZ // Emacs will see this and not \\=`undef M_BAZ
- \\=`endif
- ...
- /*AUTOUNDEF*/
+ \\=`define XX_FOO
+ \\=`define M_BAR(x)
+ \\=`define M_BAZ
+ ...
+ \\=`ifdef NEVER
+ \\=`undef M_BAZ // Emacs will see this and not \\=`undef M_BAZ
+ \\=`endif
+ ...
+ /*AUTOUNDEF*/
Typing \\[verilog-auto] will make this into:
- ...
- /*AUTOUNDEF*/
- // Beginning of automatic undefs
- \\=`undef XX_FOO
- \\=`undef M_BAR
- // End of automatics
+ ...
+ /*AUTOUNDEF*/
+ // Beginning of automatic undefs
+ \\=`undef M_BAR
+ \\=`undef XX_FOO
+ // End of automatics
You may also provide an optional regular expression, in which case only
defines the regular expression will be undefed."
An example of making a stub for another module:
- module ExampStub (/*AUTOINST*/);
- /*AUTOINOUTPARAM(\"Examp\")*/
- /*AUTOINOUTMODULE(\"Examp\")*/
- /*AUTOTIEOFF*/
- // verilator lint_off UNUSED
- wire _unused_ok = &{1\\='b0,
- /*AUTOUNUSED*/
- 1\\='b0};
- // verilator lint_on UNUSED
- endmodule
+ module ExampMain
+ (input unused_input_a, input unused_input_b);
+ endmodule
+
+ module ExampStub2 (/*AUTOARG*/);
+ /*AUTOINOUTPARAM(\"ExampMain\")*/
+ /*AUTOINOUTMODULE(\"ExampMain\")*/
+
+ /*AUTOTIEOFF*/
+
+ // verilator lint_off UNUSED
+ wire _unused_ok = &{1\\='b0,
+ /*AUTOUNUSED*/
+ 1\\='b0};
+ // verilator lint_on UNUSED
+ endmodule
Typing \\[verilog-auto] will make this into:
- ...
- // verilator lint_off UNUSED
- wire _unused_ok = &{1\\='b0,
- /*AUTOUNUSED*/
- // Beginning of automatics
- unused_input_a,
- unused_input_b,
- unused_input_c,
- // End of automatics
- 1\\='b0};
- // verilator lint_on UNUSED
- endmodule"
+ ...
+ // verilator lint_off UNUSED
+ wire _unused_ok = &{1\\='b0,
+ /*AUTOUNUSED*/
+ // Beginning of automatics
+ unused_input_a,
+ unused_input_b
+ // End of automatics
+ 1\\='b0};
+ // verilator lint_on UNUSED
+ endmodule"
(interactive)
(save-excursion
;; Find beginning
An example:
- //== State enumeration
- parameter [2:0] // auto enum state_info
- SM_IDLE = 3\\='b000,
- SM_SEND = 3\\='b001,
- SM_WAIT1 = 3\\='b010;
- //== State variables
- reg [2:0] /* auto enum state_info */
- state_r; /* auto state_vector state_r */
- reg [2:0] /* auto enum state_info */
- state_e1;
+ //== State enumeration
+ parameter [2:0] // auto enum state_info
+ SM_IDLE = 3\\='b000,
+ SM_SEND = 3\\='b001,
+ SM_WAIT1 = 3\\='b010;
+ //== State variables
+ reg [2:0] /* auto enum state_info */
+ state_r; /* auto state_vector state_r */
+ reg [2:0] /* auto enum state_info */
+ state_e1;
- /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
+ /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
Typing \\[verilog-auto] will make this into:
- ... same front matter ...
-
- /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
- // Beginning of automatic ASCII enum decoding
- reg [39:0] state_ascii_r; // Decode of state_r
- always @(state_r) begin
- case ({state_r})
- SM_IDLE: state_ascii_r = \"idle \";
- SM_SEND: state_ascii_r = \"send \";
- SM_WAIT1: state_ascii_r = \"wait1\";
- default: state_ascii_r = \"%Erro\";
- endcase
- end
- // End of automatics"
+ ...
+ /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [39:0] state_ascii_r; // Decode of state_r
+ always @(state_r) begin
+ case ({state_r})
+ SM_IDLE: state_ascii_r = \"idle \";
+ SM_SEND: state_ascii_r = \"send \";
+ SM_WAIT1: state_ascii_r = \"wait1\";
+ default: state_ascii_r = \"%Erro\";
+ endcase
+ end
+ // End of automatics"
(save-excursion
(let* ((params (verilog-read-auto-params 2 4))
(undecode-name (nth 0 params))
called before and after this function, respectively.
For example:
- module ModuleName (/*AUTOARG*/);
- /*AUTOINPUT*/
- /*AUTOOUTPUT*/
- /*AUTOWIRE*/
- /*AUTOREG*/
- InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
+ module ExampModule (/*AUTOARG*/);
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ /*AUTOWIRE*/
+ /*AUTOREG*/
+ InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
+ endmodule
You can also update the AUTOs from the shell using:
emacs --batch <filenames.v> -f verilog-batch-auto
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