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(parent: 9b93e3b) | patch
Fix regular-expression glitches and typos. Update verilog-mode from upstream.
authorWilson Snyder <wsnyder@wsnyder.org>
Tue, 5 Mar 2019 14:46:36 +0000 (09:46 -0500)
committerWilson Snyder <wsnyder@wsnyder.org>
Tue, 5 Mar 2019 14:47:00 +0000 (09:47 -0500)
commitc5c2acd1c605243da7f8b9c4cd41ebdb0e9a7a38
tree57e687f78fb14768b441ebb75a9618e69510d80btree | snapshot
parent9b93e3b0759d562989283eaecf32e075f984c18ccommit | diff
Fix regular-expression glitches and typos. Update verilog-mode from upstream.

* lisp/progmodes/verilog-mode.el (verilog-read-decls): Fix AUTO vectors with
double brackets, msg2839.
(verilog-read-auto-template-middle): Fix AUTO_TEMPLATE with regexp
capture group reference, but1379.  Reported by David Rogoff.
lisp/progmodes/verilog-mode.el diff | blob | history
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