Verilog-mode update from upstream https://github.com/veripool/verilog-mode

Verilog-mode update from upstream https://github.com/veripool/verilog-mode

* lisp/progmodes/verilog-mode.el (verilog-auto-inst)
(verilog-auto-inst-param): Remove intended formfeeds.  Our ability to
detect unintended formfeeds elsewhere outweighs their limited utility here.
Contributed by Mattias Engdegård.
(verilog-at-constraint-p)
(verilog-at-struct-mv-p, verilog-at-struct-p, verilog-calc-1)
(verilog-in-case-region-p, verilog-in-fork-region-p)
(verilog-in-generate-region-p, verilog-set-auto-endcomments):
Fix indentation problem when there is a signal named "module_something"
(#1861).  Cleanup RexEx groupings.
(verilog-read-sub-decls-expr):
Fix apostrophe parser in AUTOWIRE (#1854) (#1855).
(verilog-auto-inst-port): Fix AUTOINST
multi-dimensional array [] substitution.  Reported by Caleb Begly.
(verilog-property-re, verilog-beg-of-statement, verilog-calc-1):
Concurrent SVA statement pattern-matching learns 'restrict property' and
'cover sequence' expression for proper indentation around those constructs. This
addresses more patterns in IEEE 1800-2017's 'concurrent_sasertion_statement'
grammar.
(verilog-read-sub-decls-line):
Fix `verilog-auto-ignore-concat' with parenthesis signals.
Reported by Dmitri Sorkin.
(verilog-simplify-range-expression): Fix
`verilog-auto-inst-param-value' confusing structure selects.
Reported by Mike Bertone.

(cherry picked from commit b2d18ff944ae374fa03579ca2574f1fba8ae2e4b)