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(parent: a35e06b) | patch
Rename variable for clarity
authorMattias Engdegård <mattiase@acm.org>
Sun, 7 Apr 2019 18:50:40 +0000 (20:50 +0200)
committerMattias Engdegård <mattiase@acm.org>
Sun, 7 Apr 2019 18:51:00 +0000 (20:51 +0200)
commit6dfe231c3197971fc0cdddcc1299200da80f3729
treec9105c3bf00fd2064d6c9ae7c14691886cfd04a8tree | snapshot
parenta35e06bbe27c5907f56c5aeb48182d7be00d1deccommit | diff
Rename variable for clarity

* lisp/progmodes/verilog-mode.el (verilog-sk-define-signal):
Rename sig-re to sig-chars, to make it clear that it isn't a regexp.
lisp/progmodes/verilog-mode.el diff | blob | history
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