]> git.eshelyaron.com Git - emacs.git/commit
* progmodes/verilog-mode.el (verilog-auto-inout-module):
authorDan Nicolaescu <dann@ics.uci.edu>
Fri, 28 Mar 2008 15:47:25 +0000 (15:47 +0000)
committerDan Nicolaescu <dann@ics.uci.edu>
Fri, 28 Mar 2008 15:47:25 +0000 (15:47 +0000)
commit1dd4b004656363e5c8e8d8090f120e9b7905c776
tree8bb895ae9d01c994744b64b9e0456e2348444870
parent0d22595df58136551ee4e6a8f54d71034e3a73ee
* progmodes/verilog-mode.el (verilog-auto-inout-module):
Add optional regular expression to AUTOINOUTMODULE.
(verilog-inject-auto, verilog-auto-arg, verilog-auto-inst)
(verilog-auto-inst-param, verilog-auto-reg)
(verilog-auto-reg-input, verilog-auto-wire, verilog-auto-output)
(verilog-auto-output-every, verilog-auto-input)
(verilog-auto-inout, verilog-auto-sense, verilog-auto-tieoff)
(verilog-auto-unused, verilog-auto): Update documentation to use
more obvious instance module names versus cell names.
lisp/ChangeLog
lisp/progmodes/verilog-mode.el